| Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors DM Brooks, P Bose, SE Schuster, H Jacobson, PN Kudva, ... IEEE Micro 20 (6), 26-44, 2000 | 649 | 2000 |
| Environment for PowerPC microarchitecture exploration M Moudgill, JD Wellman, JH Moreno IEEE Micro 19 (3), 15-25, 1999 | 152 | 1999 |
| Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism ER Altman, PG Capek, M Gschwind, HP Hofstee, JA Kahle, R Nair, ... US Patent 6,779,049, 2004 | 110 | 2004 |
| Method and apparatus for memory prefetching based on intra-page usage history JH Moreno, JA Rivers, JD Wellman US Patent 6,678,795, 2004 | 70 | 2004 |
| Implementing instruction set architectures with non-contiguous register file specifiers MK Gschwind, RK Montoye, B Olsson, JD Wellman US Patent 7,793,081, 2010 | 68 | 2010 |
| Implementing instruction set architectures with non-contiguous register file specifiers MK Gschwind, RK Montoye, B Olsson, JD Wellman US Patent 7,421,566, 2008 | 66 | 2008 |
| Implementing instruction set architectures with non-contiguous register file specifiers MK Gschwind, RK Montoye, B Olsson, JD Wellman US Patent 8,166,281, 2012 | 54 | 2012 |
| Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors ER Altman, PG Capek, M Gschwind, HP Hofstee, JA Kahle, R Nair, ... US Patent 6,907,477, 2005 | 53 | 2005 |
| Power-performance modeling and tradeoff analysis for a high end microprocessor D Brooks, M Martonosi, JD Wellman, P Bose Power-Aware Computer Systems: First International Workshop, PACS 2000 …, 2001 | 50 | 2001 |
| Implementing instruction set architectures with non-contiguous register file specifiers MK Gschwind, RK Montoye, B Olsson, JD Wellman US Patent 8,918,623, 2014 | 47 | 2014 |
| Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture E Altman, M Gschwind, D Prener, J Rivers, S Sathaye, JD Wellman, ... US Patent App. 11/047,983, 2006 | 47 | 2006 |
| System and method of execution of register pointer instructions ahead of instruction issues E Altman, MK Gschwind, JA Rivers, SW Sathaye, JD Wellman, V Zyuban US Patent 7,496,733, 2009 | 37 | 2009 |
| Methods for generating code for an architecture encoding an extended register specification M Gschwind, R Montoye, B Olsson, JD Wellman US Patent App. 11/446,031, 2007 | 34 | 2007 |
| Control signal memoization in a multiple instruction issue microprocessor ER Altman, MK Gschwind, JA Rivers, SW Sathaye, JD Wellman, ... US Patent 8,151,092, 2012 | 30 | 2012 |
| Token based DMA HP Hofstee, R Nair, JD Wellman US Patent 6,820,142, 2004 | 30 | 2004 |
| Transient cache storage with discard function for disposable data ER Altman, MK Gschwind, RK Montoye, JA Rivers, SW Sathaye, ... US Patent 7,461,209, 2008 | 28 | 2008 |
| Phaser: Phased methodology for modeling the system-level effects of soft errors JA Rivers, P Bose, P Kudva, JD Wellman, PN Sanda, EH Cannon, ... IBM Journal of Research and Development 52 (3), 293-306, 2008 | 27 | 2008 |
| Evaluating the communication performance of MPPs using synthetic sparse matrix multiplication workloads EL Boyd, JD Wellman, SG Abraham, ES Davidson Proceedings of the 7th international conference on Supercomputing, 240-250, 1993 | 27 | 1993 |
| System and structure for synchronized thread priority selection in a deeply pipelined multithreaded microprocessor P Kudva, DS Levitan, B Sinharoy, JD Wellman US Patent App. 11/737,491, 2008 | 26 | 2008 |
| Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching JH Moreno, JA Rivers, JD Wellman US Patent 6,711,651, 2004 | 24 | 2004 |
