Da-Cheng Juan
Da-Cheng Juan
Google Research, Carnegie Mellon University
Verified email at dacheng.info
Title
Cited by
Cited by
Year
Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling
DC Juan, S Garg, J Park, D Marculescu
2013 International Conference on Hardware/Software Codesign and System …, 2013
452013
Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors
DC Juan, D Marculescu
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
392012
Dpp-net: Device-aware progressive search for pareto-optimal neural architectures
JD Dong, AC Cheng, DC Juan, W Wei, M Sun
Proceedings of the European Conference on Computer Vision (ECCV), 517-531, 2018
362018
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization
DS Chiou, DC Juan, YT Chen, SC Chang
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 81 - 86, 2007
362007
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
YT Chen, DC Juan, MC Lee, SC Chang
2007 IEEE/ACM International Conference on Computer-Aided Design, 779-782, 2007
342007
Svr-noc: A performance analysis tool for network-on-chips using learning-based support vector regression model
Z Qian, DC Juan, P Bogdan, CY Tsui, D Marculescu, R Marculescu
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 354-357, 2013
312013
Monas: Multi-objective neural architecture search using reinforcement learning
CH Hsu, SH Chang, JH Liang, HP Chou, CH Liu, SC Chang, JY Pan, ...
arXiv preprint arXiv:1806.10332, 2018
302018
A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors
DC Juan, H Zhou, D Marculescu, X Li
17th Asia and South Pacific Design Automation Conference, 597-602, 2012
302012
An efficient wake-up strategy considering spurious glitches phenomenon for power gating designs
DC Juan, YT Chen, MC Lee, SC Chang
IEEE transactions on very large scale integration (VLSI) systems 18 (2), 246-255, 2009
292009
Neuralpower: Predict and deploy energy-efficient convolutional neural networks
E Cai, DC Juan, D Stamoulis, D Marculescu
arXiv preprint arXiv:1710.05420, 2017
282017
A comprehensive and accurate latency model for network-on-chip performance analysis
Z Qian, DC Juan, P Bogdan, CY Tsui, D Marculescu, R Marculescu
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 323-328, 2014
252014
A support vector regression (SVR)-based latency model for network-on-chip (NoC) architectures
ZL Qian, DC Juan, P Bogdan, CY Tsui, D Marculescu, R Marculescu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
242015
Beyond poisson: Modeling inter-arrival time of requests in a datacenter
DC Juan, L Li, HK Peng, D Marculescu, C Faloutsos
Pacific-Asia Conference on Knowledge Discovery and Data Mining, 198-209, 2014
212014
Hyperpower: Power-and memory-constrained hyper-parameter optimization for neural networks
D Stamoulis, E Cai, DC Juan, D Marculescu
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 19-24, 2018
202018
Statistical peak temperature prediction and thermal yield improvement for 3D chip multiprocessors
DC Juan, S Garg, D Marculescu
ACM Transactions on Design Automation of Electronic Systems (TODAES) 19 (4 …, 2014
202014
Statistical thermal evaluation and mitigation techniques for 3D chip-multiprocessors in the presence of process variations
DC Juan, S Garg, D Marculescu
2011 Design, Automation & Test in Europe, 1-6, 2011
192011
A context-aware user-item representation learning for item recommendation
L Wu, C Quan, C Li, Q Wang, B Zheng, X Luo
ACM Transactions on Information Systems (TOIS) 37 (2), 1-29, 2019
162019
Phase analysis and identification method for multiphase batch processes with partitioning multi-way principal component analysis (MPCA) model
D Weiwei, Y Yuan, GAO Furong
Chinese Journal of Chemical Engineering 20 (6), 1121-1127, 2012
152012
Learning-based power/performance optimization for many-core systems with extended-range voltage/frequency scaling
E Cai, DC Juan, S Garg, J Park, D Marculescu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
142015
Ppp-net: Platform-aware progressive search for pareto-optimal neural architectures
JD Dong, AC Cheng, DC Juan, W Wei, M Sun
132018
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