| Development of 3-D silicon module with TSV for system in packaging N Khan, VS Rao, S Lim, HS We, V Lee, X Zhang, EB Liao, R Nagarajan, ... IEEE Transactions on Components and Packaging Technologies 33 (1), 3-9, 2010 | 204 | 2010 |
| Development of through silicon via (TSV) interposer technology for large die (21× 21mm) fine-pitch Cu/low-k FCBGA package X Zhang, TC Chai, JH Lau, CS Selvanayagam, K Biswas, S Liu, D Pinjala, ... 2009 59th Electronic components and technology conference, 305-312, 2009 | 133 | 2009 |
| Electromigration in flip chip solder joints having a thick Cu column bump and a shallow solder interconnect JW Nah, JO Suh, KN Tu, SW Yoon, VS Rao, V Kripesh, F Hua Journal of applied physics 100 (12), 2006 | 123 | 2006 |
| Development of high density fan out wafer level package (HD FOWLP) with multi-layer fine pitch RDL for mobile applications VS Rao, CT Chong, D Ho, DM Zhi, CS Choong, LPS Sharon, D Ismael, ... 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 1522-1529, 2016 | 118 | 2016 |
| TSV interposer fabrication for 3D IC packaging VS Rao, HS Wee, LWS Vincent, LH Yu, L Ebin, R Nagarajan, CT Chong, ... 2009 11th Electronics Packaging Technology Conference, 431-437, 2009 | 86 | 2009 |
| A novel method to predict die shift during compression molding in embedded wafer level package CH Khong, A Kumar, X Zhang, G Sharma, SR Vempati, K Vaidyanathan, ... 2009 59th Electronic Components and Technology Conference, 535-541, 2009 | 55 | 2009 |
| Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects SR Vempati, N Su, CH Khong, YY Lim, K Vaidyanathan, JH Lau, BP Liew, ... 2009 59th Electronic Components and Technology Conference, 980-987, 2009 | 55 | 2009 |
| A thick photoresist process for advanced wafer level packaging applications using JSR THB-151N negative tone UV photoresist VS Rao, V Kripesh, SW Yoon, AAO Tay Journal of Micromechanics and Microengineering 16 (9), 1841, 2006 | 50 | 2006 |
| Copper interconnections for high performance and fine pitch flip chip digital applications and ultra-miniaturized RF module applications RR Tummala, PM Raj, A Aggarwal, G Mehrotra, SW Koh, S Bansal, ... 56th Electronic Components and Technology Conference 2006, 10 pp., 2006 | 42 | 2006 |
| Process development and reliability of microbumps SPS Lim, VS Rao, WY Hnin, WL Ching, V Kripesh, C Lee, J Lau, J Milla, ... IEEE transactions on Components and Packaging Technologies 33 (4), 747-753, 2010 | 37 | 2010 |
| Electromigration study of 50 µm pitch micro solder bumps using four-point Kelvin structure DQ Yu, TC Chai, ML Thew, YY Ong, VS Rao, LC Wai, JH Lau 2009 59th Electronic Components and Technology Conference, 930-935, 2009 | 35 | 2009 |
| Variability, correlation and path studies in coloured rice KS Singh, Y Suneetha, GV Kumar, VS Rao, DS Raja, T Srinivas Int J Chem Stud 8 (4), 2138-2144, 2020 | 33 | 2020 |
| Development of coaxial shield via in silicon carrier for high frequency application SW Ho, VS Rao, OKN Khan, SU Yoon, V Kripesh 2006 8th Electronics Packaging Technology Conference, 825-830, 2006 | 33 | 2006 |
| Process and reliability of large fan-out wafer level package based package-on-package VS Rao, CT Chong, D Ho, DM Zhi, CS Choong, SL PS, D Ismael, ... 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 615-622, 2017 | 31 | 2017 |
| Development of package-on-package using embedded wafer-level package approach SC Chong, DHS Wee, VS Rao, NS Vasarla IEEE Transactions on Components, Packaging and Manufacturing Technology 3 …, 2013 | 27 | 2013 |
| Process and reliability assessment of 200μm-thin embedded wafer level packages (EMWLPs) HJ Kim, SC Chong, DSW Ho, EWY Yong, CH Khong, CWL Teo, ... 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 78-83, 2011 | 27 | 2011 |
| Process challenges and development of eWLP SC Chong, CH Khong, KLC Sing, DHS Wee, CTW Liang, VLW Sheng, ... 2010 12th Electronics Packaging Technology Conference, 527-531, 2010 | 25 | 2010 |
| Study on silver sintered die attach material with different metal surfaces for high temperature and high pressure (300° c/30kpsi) applications LC Wai, WW Seit, EPJ Rong, MZ Ding, VS Rao, DR MinWoo 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013), 335-340, 2013 | 23 | 2013 |
| Bed of nails-100 microns pitch wafer level interconnections process VS Rao, AAO Tay, V Kripesh, CT Lim, SW Yoon Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004 …, 2004 | 23 | 2004 |
| Genetic divergence studies in rice (Oryza sativa L.) hyrids for yield, yield component traits and quality parameters M Devi, DPB Jyothula, B Krishnaveni, VS Rao Int. J. Curr. Microbiol. App. Sci 8 (6), 1577-1583, 2019 | 22 | 2019 |
