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Raul Garcia Ordaz
Raul Garcia Ordaz
Verified email at arm.com - Homepage
Title
Cited by
Cited by
Year
soft-NEON: A study on replacing the NEON engine of an ARM SoC with a reconfigurable fabric
JRG Ordaz, D Koch
2016 IEEE 27th International Conference on Application-specific Systems …, 2016
82016
A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine
JRG Ordaz, D Koch
2018 IEEE 29th International Conference on Application-specific Systems …, 2018
72018
A reorder buffer design for high performance processors
JRG Ordaz, MAR Salinas, LAV Vargas, HM Lozano, CP Macías
Computación y Sistemas 16 (1), 15-25, 2012
52012
A security library for FPGA interlays
A Vaishnav, JRG Ordaz, D Koch
2017 27th International Conference on Field Programmable Logic and …, 2017
32017
On the HLS Design of Bit-Level Operations and Custom Data Types
JRG Ordaz, D Koch
FSP 2017; Fourth International Workshop on FPGAs for Software Programmers, 1-8, 2017
22017
Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit
JRG Ordaz, D Koch
2017 27th International Conference on Field Programmable Logic and …, 2017
22017
DYNAMIC CPU ISA CUSTOMIZATIONS THROUGH FPGA INTERLAYS
JR Garcia Ordaz
https://www.research.manchester.ac.uk/portal/en/theses/dynamic-cpu-isa …, 2018
2018
HLS Compilation for CPU Interlays
JRG Ordaz, D Koch
Proceedings of the 8th International Symposium on Highly Efficient …, 2017
2017
Diseño de un búfer de reordenamiento para procesadores de alto desempeño
JR García Ordaz, MA Ramírez Salinas, LA Villa Vargas, H Molina Lozano, ...
Computación y Sistemas 16 (1), 15-25, 2012
2012
Diseño de un ROB-Distribuido para procesadores superescalables
JR García Ordaz
Instituto Politécnico Nacional. Centro de Investigación en Computación, 2011
2011
Diseño de un ROB-Distribuido para Procesadores Superescalares
JRG Ordaz
Instituto Politécnico Nacional, 2010
2010
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Articles 1–11