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Sukanta Dey
Sukanta Dey
Intel Corporation, Santa Clara, CA, US
在 intel.com 的电子邮件经过验证 - 首页
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EvadePDF: Towards Evading Machine Learning Based PDF Malware Classifiers
S Dey, A Kumar, M Sawarkar, PK Singh, S Nandi
International Conference on Security & Privacy, 140-150, 2019
222019
PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning
S Dey, S Nandi, G Trivedi
2020 IEEE/ACM Design, Automation & Test in Europe Conference (DATE), 1520-1525, 2020
182020
Energy Efficient Approach to Detect Sinkhole Attack Using Roving IDS in 6LoWPAN Network
P Bhale, S Dey, S Biswas, S Nandi
20th International Conference on Innovations for Community Services, 187-207, 2020
182020
Machine learning approach for fast electromigration aware aging prediction in incremental design of large scale on-chip power grid network
S Dey, S Nandi, G Trivedi
ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (5 …, 2020
152020
PGIREM: Reliability-constrained IR drop minimization and electromigration assessment of VLSI power grid networks using cooperative coevolution
S Dey, S Dash, S Nandi, G Trivedi
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 40-45, 2018
132018
Secure Physical Design
S Dey, J Park, N Pundir, D Saha, AM Shuvo, D Mehta, N Asadi, F Rahman, ...
Cryptology ePrint Archive, 2022
122022
Machine learning for VLSI CAD: A case study in on-chip power grid design
S Dey, S Nandi, G Trivedi
2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 378-383, 2021
122021
PGOpt: Multi-objective Design Space Exploration Framework for Large-Scale On-Chip Power Grid Design in VLSI SoC using Evolutionary Computing Technique
S Dey, S Nandi, G Trivedi
Microprocessors and Microsystems 81, 103440, 2021
122021
PGRDP: Reliability, Delay, and Power-Aware Area Minimization of Large-Scale VLSI Power Grid Network Using Cooperative Coevolution
S Dey, S Nandi, G Trivedi
Intelligent Computing Paradigm: Recent Trends, 69-84, 2020
82020
Markov chain model using lévy flight for VLSI power grid analysis
S Dey, S Dash, S Nandi, G Trivedi
2017 30th International Conference on VLSI Design (VLSID), 107-112, 2017
82017
ReFIT: Reliability Challenges and Failure Rate Mitigation Techniques for IoT Systems
S Dey, S Nandi
20th International Conference on Innovations for Community Services, 123-142, 2020
62020
Minimizing area of VLSI power distribution networks using river formation dynamics
S Dash, S Dey, D Joshi, G Trivedi
Journal of Systems and Information Technology 20 (4), 417-429, 2018
62018
Design Methodology for OnChip Power Grid Interconnect: Al/ML Perspective
S Dey
IIT Guwahati, 2021
32021
RiverOpt: A Multiobjective Optimization Framework Based on Modified River Formation Dynamics Heuristic
S Dash, S Dey, A Augustine, RS Dhar, J Pidanic, Z Nemec, G Trivedi
32nd IEEE/ACM International Conference on VLSI Design (VLSID), 233-238, 2019
12019
Physically-aware Laser Fault Injection Assessment
H Li, S Dey, F Farahmandi
Government Microcircuit Applications & Critical Technology Conference …, 2023
2023
JSpongeGen: A Pseudo Random Generator for Low Resource Devices
PK Singh, AV Monsy, R Garg, S Dey, S Nandi
Distributed Computing and Internet Technology: 15th International Conference …, 2019
2019
StormOptimus: A Single Objective Constrained Optimizer Based on Brainstorming Process for VLSI Circuits
S Dash, D Joshi, S Dey, M Janveja, G Trivedi
Brain Storm Optimization Algorithms: Concepts, Principles and Applications …, 2019
2019
Analysis and Optimization of Reliability Issues of VLSI Power Grid Networks
S Dey
2019 IEEE/ACM Design, Automation & Test in Europe Conference (DATE), Ph.D. Forum, 2019
2019
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