| Scalable packet classification on FPGA W Jiang, VK Prasanna IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (9 …, 2011 | 189 | 2011 |
| Compact architecture for high-throughput regular expression matching on FPGA YHE Yang, W Jiang, VK Prasanna Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking …, 2008 | 175 | 2008 |
| Beyond TCAMs: An SRAM-based parallel multi-pipeline architecture for terabit IP lookup W Jiang, Q Wang, VK Prasanna IEEE INFOCOM 2008-The 27th Conference on Computer Communications, 1786-1794, 2008 | 135 | 2008 |
| Large-scale wire-speed packet classification on FPGAs W Jiang, VK Prasanna Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2009 | 134 | 2009 |
| Scalable ternary content addressable memory implementation using FPGAs W Jiang Architectures for Networking and Communications Systems, 71-82, 2013 | 112 | 2013 |
| Field-split parallel architecture for high performance multi-match packet classification using FPGAs W Jiang, VK Prasanna Proceedings of the twenty-first annual symposium on Parallelism in …, 2009 | 103 | 2009 |
| ParaSplit: A scalable architecture on FPGA for terabit packet classification J Fong, X Wang, Y Qi, J Li, W Jiang 2012 IEEE 20th Annual Symposium on High-Performance Interconnects, 1-8, 2012 | 91 | 2012 |
| High-speed packet processing using reconfigurable computing G Brebner, W Jiang IEEE Micro 34 (1), 8-18, 2014 | 81 | 2014 |
| Optimizing routing metrics for large-scale multi-radio mesh networks W Jiang, S Liu, Y Zhu, Z Zhang 2007 International Conference on Wireless Communications, Networking and …, 2007 | 77 | 2007 |
| Multi-dimensional packet classification on FPGA: 100 Gbps and beyond Y Qi, J Fong, W Jiang, B Xu, J Li, V Prasanna 2010 International Conference on Field-Programmable Technology, 241-248, 2010 | 69 | 2010 |
| Real-time classification of multimedia traffic using FPGA W Jiang, M Gokhale 2010 International Conference on Field Programmable Logic and Applications …, 2010 | 67 | 2010 |
| A scalable and modular architecture for high-performance packet classification T Ganegedara, W Jiang, VK Prasanna IEEE Transactions on Parallel and Distributed Systems 25 (5), 1135-1144, 2013 | 66 | 2013 |
| A memory-balanced linear pipeline architecture for trie-based IP lookup W Jiang, VK Prasanna 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007), 83-90, 2007 | 65 | 2007 |
| A sram-based architecture for trie-based ip lookup using fpga H Le, W Jiang, VK Prasanna 2008 16th International Symposium on Field-Programmable Custom Computing …, 2008 | 56 | 2008 |
| Feacan: Front-end acceleration for content-aware network processing Y Qi, K Wang, J Fong, Y Xue, J Li, W Jiang, V Prasanna 2011 Proceedings IEEE INFOCOM, 2114-2122, 2011 | 53 | 2011 |
| Scalable multi-pipeline architecture for high performance multi-pattern string matching W Jiang, YHE Yang, VK Prasanna 2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010 | 52 | 2010 |
| A FPGA-based parallel architecture for scalable high-speed packet classification W Jiang, VK Prasanna 2009 20th IEEE International Conference on Application-specific Systems …, 2009 | 50 | 2009 |
| Parallel IP lookup using multiple SRAM-based pipelines W Jiang, VK Prasanna 2008 IEEE International Symposium on Parallel and Distributed Processing, 1-14, 2008 | 45 | 2008 |
| Scalable high-throughput sram-based architecture for ip-lookup using FPGA H Le, W Jiang, VK Prasanna 2008 International Conference on Field Programmable Logic and Applications …, 2008 | 42 | 2008 |
| Practical multituple packet classification using dynamic discrete bit selection B Yang, J Fong, W Jiang, Y Xue, J Li IEEE Transactions on Computers 63 (2), 424-434, 2012 | 41 | 2012 |
Viktor K. PrasannaUniversity of Southern CaliforniaVerified email at usc.edu
