| Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress TA Brunner, VC Menon, CW Wong, O Gluschenkov, MP Belyansky, ... Journal of Micro/Nanolithography, MEMS, and MOEMS 12 (4), 043002-043002, 2013 | 57 | 2013 |
| Predicting distortions and overlay errors due to wafer deformation during chucking on lithography scanners KT Turner, S Veeraraghavan, JK Sinha Journal of Micro/Nanolithography, MEMS and MOEMS 8 (4), 043015-043015-8, 2009 | 50 | 2009 |
| Site based quantification of substrate topography and its relation to lithography defocus and overlay S Veeraraghavan, J Sinha US Patent 8,768,665, 2014 | 39 | 2014 |
| Overlay and semiconductor process control using a wafer geometry metric P Vukkadala, S Veeraraghavan, JK Sinha US Patent 9,354,526, 2016 | 36 | 2016 |
| Relationship between localized wafer shape changes induced by residual stress and overlay errors KT Turner, S Veeraraghavan, JK Sinha Journal of Micro/Nanolithography, MEMS, and MOEMS 11 (1), 013001-013001, 2012 | 34 | 2012 |
| Process-induced distortion prediction and feedforward and feedback correction of overlay errors P Vukkadala, H Chen, J Sinha, S Veeraraghavan US Patent 10,401,279, 2019 | 24 | 2019 |
| Characterization and mitigation of overlay error on silicon wafers with nonuniform stress T Brunner, V Menon, C Wong, N Felix, M Pike, O Gluschenkov, ... Optical Microlithography XXVII 9052, 242-253, 2014 | 22 | 2014 |
| System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking P Vukkadala, S Veeraraghavan, J Sinha, H Chen, M Kirk US Patent 9,430,593, 2016 | 20 | 2016 |
| Monitoring process-induced overlay errors through high-resolution wafer geometry measurements KT Turner, P Vukkadala, S Veeraraghavan, JK Sinha Metrology, Inspection, and Process Control for Microlithography XXVIII 9050 …, 2014 | 16 | 2014 |
| Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool H Chen, J Sinha, S Kamensky, S Veeraraghavan, P Vukkadala US Patent 9,546,862, 2017 | 15 | 2017 |
| Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes J Peterson, G Rusk, S Veeraraghavan, K Huang, T Koffas, P Kimani, ... Metrology, Inspection, and Process Control for Microlithography XXIX 9424 …, 2015 | 15 | 2015 |
| Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices H Lee, J Lee, SM Kim, C Lee, S Han, M Kim, W Kwon, SK Park, ... Metrology, Inspection, and Process Control for Microlithography XXIX 9424 …, 2015 | 14 | 2015 |
| Localized substrate geometry characterization S Veeraraghavan, JK Sinha, R Fettig US Patent 8,065,109, 2011 | 13 | 2011 |
| Improvement of depth of focus control using wafer geometry H Lee, J Lee, S Kim, C Lee, S Han, M Kim, W Kwon, SK Park, ... Metrology, Inspection, and Process Control for Microlithography XXIX 9424 …, 2015 | 11 | 2015 |
| Electrostatic chucking for extreme ultraviolet lithography: Simulations and experiments M Nataraju, J Sohn, S Veeraraghavan, AR Mikkelson, KT Turner, ... Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2006 | 11 | 2006 |
| System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking P Vukkadala, S Veeraraghavan, J Sinha, H Chen, M Kirk US Patent 10,025,894, 2018 | 10 | 2018 |
| DPL Overlay Component VR Nagaswami, J Sinha, S Veeraraghavan, F Laske, A Golotsvan, D Tien, ... 6th Intl. Symp. On Immersion Lithography, 2009 | 10 | 2009 |
| Breakdown analysis of geometry induced overlay and utilization of breakdown analysis for improved overlay control S Veeraraghavan, CC Huang US Patent 10,509,329, 2019 | 9 | 2019 |
| Using wafer geometry to improve scanner correction effectiveness for overlay control C MacNaughton, S Veeraraghavan, P Vukkadala, J Sinha, A Azordegan US Patent 9,029,810, 2015 | 8 | 2015 |
| Overlay and semiconductor process control using a wafer geometry metric P Vukkadala, S Veeraraghavan, JK Sinha US Patent 10,249,523, 2019 | 7 | 2019 |
