| Interconnect analysis and synthesis S Lin, JP Lillis John Wiley & Sons, Inc., 1999 | 415 | 1999 |
| Optimal wire sizing and buffer insertion for low power and a generalized delay model J Lillis, CK Cheng, TTY Lin IEEE Journal of Solid-State Circuits 31 (3), 437-447, 1996 | 407 | 1996 |
| Mongrel: Hybrid techniques for standard cell placement SW Hur, J Lillis IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000 | 176 | 2000 |
| New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing J Lillis, CK Cheng, TTY Lin, CY Ho Proceedings of the 33rd annual Design Automation Conference, 395-400, 1996 | 169 | 1996 |
| Buffered Steiner trees for difficult instances CJ Alpert, M Hrkić, J Hu, AB Kahng, J Lillis, B Liu, ST Quay, ... Proceedings of the 2001 international symposium on Physical design, 4-9, 2001 | 90 | 2001 |
| Simultaneous routing and buffer insertion for high performance interconnect J Lillis, CK Cheng, TTY Lin Proceedings of the Sixth Great Lakes Symposium on VLSI, 148-153, 1996 | 89 | 1996 |
| Relaxation and clustering in a local search framework: application to linear placement SW Hur, J Lillis Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 360-366, 1999 | 67 | 1999 |
| Timing driven maze routing SW Hur, A Jagannathan, J Lillis Proceedings of the 1999 international symposium on Physical design, 208-213, 1999 | 58 | 1999 |
| Floorplanning automation for partial-reconfigurable fpgas via feasible placements generation M Rabozzi, GC Durelli, A Miele, J Lillis, MD Santambrogio IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 151-164, 2016 | 54 | 2016 |
| Timing optimization of FPGA placements by logic replication G Beraudo, J Lillis Proceedings of the 40th annual Design Automation Conference, 196-201, 2003 | 47 | 2003 |
| Optimal and efficient buffer insertion and wire sizing J Lillis, CK Cheng, TTY Lin Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 259-262, 1995 | 47 | 1995 |
| An approach to placement-coupled logic replication M Hrkić, J Lillis, G Beraudo Proceedings of the 41st annual Design Automation Conference, 711-716, 2004 | 46 | 2004 |
| Floorplanning for partially-reconfigurable FPGA systems via mixed-integer linear programming M Rabozzi, J Lillis, MD Santambrogio 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014 | 44 | 2014 |
| A fast algorithm for context-aware buffer insertion A Jagannathan, SW Hur, J Lillis ACM Transactions on Design Automation of Electronic Systems (TODAES) 7 (1 …, 2002 | 43 | 2002 |
| S-tree: A technique for buffered routing tree synthesis M Hrkić, J Lillis Proceedings of the 39th annual Design Automation Conference, 578-583, 2002 | 42 | 2002 |
| Timing optimization for multi-source nets: Characterization and optimal repeater insertion J Lillis, CK Cheng Proceedings of the 34th annual Design Automation Conference, 214-219, 1997 | 42 | 1997 |
| Optimum prefix adders in a comprehensive area, timing and power design space J Liu, Y Zhu, H Zhu, CK Cheng, J Lillis 2007 Asia and South Pacific Design Automation Conference, 609-615, 2007 | 41 | 2007 |
| Linear decomposition algorithm for VLSI design applications J Li, J Lillis, CK Cheng Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995 | 36 | 1995 |
| Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages M Hrkić, J Lillis Proceedings of the 2002 international symposium on Physical design, 98-103, 2002 | 34 | 2002 |
| An LP-based methodology for improved timing-driven placement Q Wang, J Lillis, S Sanyal Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 30 | 2005 |
