Fabian Schuiki
Fabian Schuiki
Verified email at iis.ee.ethz.ch - Homepage
Cited by
Cited by
A scalable near-memory architecture for training deep neural networks on large in-memory datasets
F Schuiki, M Schaffner, FK Gürkaynak, L Benini
IEEE Transactions on Computers 68 (4), 484-497, 2018
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI
M Cavalcante, F Schuiki, F Zaruba, M Schaffner, L Benini
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (2), 530-543, 2019
Ntx: An energy-efficient streaming accelerator for floating-point generalized reduction workloads in 22 nm fd-soi
F Schuiki, M Schaffner, L Benini
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 662-667, 2019
The Floating Point Trinity: A Multi-modal Approach to Extreme Energy-Efficiency and Performance
F Zaruba, F Schuiki, S Mach, L Benini
2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019
Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads
F Zaruba, F Schuiki, T Hoefler, L Benini
arXiv preprint cs.AR/2002.10143, 2020
A 0.80 pJ/flop, 1.24 Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI
S Mach, F Schuiki, F Zaruba, L Benini
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication
A Kurth, W Rönninger, T Benz, M Cavalcante, F Schuiki, F Zaruba, ...
arXiv preprint arXiv:2009.05334, 2020
Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing
F Zaruba, F Schuiki, L Benini
arXiv preprint arXiv:2008.06502, 2020
FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing
S Mach, F Schuiki, F Zaruba, L Benini
arXiv preprint arXiv:2007.01530, 2020
Design of an open-source bridge between non-coherent burst-based and coherent cache-line-based memory systems
M Cavalcante, A Kurth, F Schuiki, L Benini
Proceedings of the 17th ACM International Conference on Computing Frontiers …, 2020
Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores
F Schuiki, F Zaruba, T Hoefler, L Benini
IEEE Transactions on Computers, 2020
Needle in a haystack: Limiting the search space in mission-aware packet forwarding for drones
M Asadpour, M Burger, F Schuiki, KA Hummel
Proceedings of the 1st International Workshop on Experiences with the Design …, 2015
Live Demonstration: Exploiting Body-Biasing for Static Corner Trimming and Maximum Energy Efficiency Operation in 22nm FDX Technology
A Di Mauro, F Zaruba, F Schuiki, S Mach, L Benini
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2020
A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing
F Zaruba, F Schuiki, L Benini
2020 IEEE Hot Chips 32 Symposium (HCS), 1-24, 2020
XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs
D Diamantopoulos, F Scheidegger, S Mach, F Schuiki, G Haugou, ...
2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2020
LLHD: a multi-level intermediate representation for hardware description languages
F Schuiki, A Kurth, T Grosser, L Benini
arXiv preprint arXiv:2004.03494, 2020
NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22 nm FD-SOI
F Schuiki, M Schaffner, L Benini
2019 International SoC Design Conference (ISOCC), 117-118, 2019
Kosmodrom: Energy Efficient Ariane Cores with Transprecision FPU in 22nm
F Schuiki, F Zaruba, S Mach, L Benini
A Mission-Aware Routing Algorithm for Micro Aerial Vehicle Networks
M Burger, F Schuiki
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