Mircea R. Stan

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Kevin SkadronHarry Douglas Forsyth Professor of Computer Science, University of VirginiaVerified email at virginia.edu
Wei HuangSamsung, Zeku, AMD, IBM, U.Va., USTCVerified email at samsung.com
Karthik SankaranarayananIntelVerified email at intel.com
John LachThe George Washington UniversityVerified email at gwu.edu
avik W ghoshProfessor, University of Virginia, Electrical EngineeringVerified email at virginia.edu
Xinfei GuoShanghai Jiao Tong UniversityVerified email at sjtu.edu.cn
Sudhanva GurumurthiFellow, AMDVerified email at amd.com
Matthew M. ZieglerIBM T.J. Watson Research CenterVerified email at us.ibm.com
SA WolfUniversity of VirginiaVerified email at virginia.edu
Wayne BurlesonUniversity of Massachusetts AmherstVerified email at ecs.umass.edu
Runjie ZhangEDA, OracleVerified email at oracle.com
Zhenyu QiVerified email at virginia.edu
Brett H MeyerAssociate Professor of ECE, McGill UniversityVerified email at mcgill.ca
Garrett S. RoseProfessor, University of TennesseeVerified email at utk.edu
Elaheh SadrediniAssistant Professor, University of California at RiversideVerified email at cs.ucr.edu
Vivek DeIntel Fellow, Intel CorporationVerified email at intel.com
Tommy Tracy IIUniversity of VirginiaVerified email at virginia.edu
Jack WaddenComputer Science, University of MichiganVerified email at umich.edu
Bhushan (Vidyabhushan) MohanUniversity of Virginia, SanDisk, WDC, Pure Storage, GrammarlyVerified email at virginia.edu
Patricia Gonzalez GuerreroGraduate student, University of VirginiaVerified email at virginia.edu

Mircea R. Stan

Virginia Microelectronics Consortium (VMEC) Professor, University of Virginia

Verified email at virginia.edu - Homepage

VLSI low power Processing-in-Memory nanoelectronics


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
Temperature-aware microarchitecture K Skadron, MR Stan, W Huang, S Velusamy, K Sankaranarayanan, ... ACM SIGARCH Computer Architecture News 31 (2), 2-13, 2003	1668	2003
Bus-invert coding for low-power I/O MR Stan, WP Burleson IEEE Transactions on very large scale integration (VLSI) systems 3 (1), 49-58, 1995	1461	1995
HotSpot: A compact thermal modeling methodology for early-stage VLSI design W Huang, S Ghosh, S Velusamy, K Sankaranarayanan, K Skadron, ... IEEE Transactions on very large scale integration (VLSI) systems 14 (5), 501-513, 2006	1304	2006
Temperature-aware microarchitecture: Modeling and implementation K Skadron, MR Stan, K Sankaranarayanan, W Huang, S Velusamy, ... ACM Transactions on Architecture and Code Optimization (TACO) 1 (1), 94-125, 2004	963	2004
Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management K Skadron, T Abdelzaher, MR Stan Proceedings Eighth International Symposium on High Performance Computer …, 2002	561	2002
Relaxing non-volatility for fast and energy-efficient STT-RAM caches CW Smullen, V Mohan, A Nigam, S Gurumurthi, MR Stan 2011 IEEE 17th International Symposium on High Performance Computer …, 2011	535	2011
Advances and future prospects of spin-transfer torque random access memory E Chen, D Apalkov, Z Diao, A Driskill-Smith, D Druist, D Lottis, V Nikitin, ... IEEE Transactions on Magnetics 46 (6), 1873-1878, 2010	519	2010
Compact thermal modeling for temperature-aware design W Huang, MR Stan, K Skadron, K Sankaranarayanan, S Ghosh, ... Proceedings of the 41st annual design automation conference, 878-883, 2004	460	2004
The promise of nanomagnetics and spintronics for future logic and universal memory SA Wolf, J Lu, MR Stan, E Chen, DM Treger Proceedings of the IEEE 98 (12), 2155-2168, 2010	416	2010
Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects Y Zhang, D Parikh, K Sankaranarayanan, K Skadron, M Stan Technical Report CS-2003-05, University of Virginia, 2003	374	2003
Molecular electronics: From devices and interconnect to circuits and architecture MR Stan, PD Franzon, SC Goldstein, JC Lach, MM Ziegler Proceedings of the IEEE 91 (11), 1940-1957, 2003	373	2003
A case for thermal-aware floorplanning at the microarchitectural level K Sankaranarayanan, S Velusamy, M Stan, K Skadron Journal of Instruction-Level Parallelism 7 (1), 8-16, 2005	264	2005
CMOS/nano co-design for crossbar-based molecular electronic systems MM Ziegler, MR Stan IEEE Transactions on Nanotechnology 2 (4), 217-230, 2003	247	2003
Low-power encodings for global communication in CMOS VLSI MR Stan, WP Burleson IEEE transactions on very large scale integration (VLSI) systems 5 (4), 444-455, 1997	237	1997
Circuit-level techniques to control gate leakage for sub-100nm CMOS F Hamzaoglu, MR Stan Proceedings of the 2002 international symposium on Low power electronics and …, 2002	190	2002
Odd/even bus invert with two-phase transfer for buses with coupling Y Zhang, J Lach, K Skadron, MR Stan Proceedings of the 2002 international symposium on Low power electronics and …, 2002	180	2002
Power issues related to branch prediction D Parikh, K Skadron, Y Zhang, M Barcella, MR Stan Proceedings Eighth International Symposium on High Performance Computer …, 2002	171	2002
Scaling with design constraints: Predicting the future of big chips W Huang, K Rajamani, MR Stan, K Skadron IEEE Micro 31 (4), 16-29, 2011	170	2011
Perfect 3-limited-weight code for low power I/O MR Stan, Y Zhang International Workshop on Power and Timing Modeling, Optimization and …, 2004	163	2004
Hotspot 6.0: Validation, acceleration and extension R Zhang, MR Stan, K Skadron University of Virginia, Tech. Rep, 2015	160	2015

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