| DRAMPower: Open-source DRAM power & energy estimation tool K Chandrasekar, C Weis, Y Li, S Goossens, M Jung, O Naji, B Akesson, ... URL: http://www.drampower.info, 2012 | 178 | 2012 |
| Virtual Execution Platforms for Mixed-Time-Criticality Applications: The CompSOC Architecture and Design Flow K Goossens, A Azevedo, K Chandrasekar, MD Gomony, S Goossens, ... | 117* | 2012 |
| Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization K Chandrasekar, SLM Goossens, C Weis, M Koedam, B Akesson, ... Proceedings of the Conference on Design, Automation and Test in Europe (DATE …, 2014 | 93 | 2014 |
| Improved power modeling of DDR SDRAMs K Chandrasekar, B Akesson, K Goossens Digital System Design (DSD), 2011 14th Euromicro Conference on, 99-108, 2011 | 93 | 2011 |
| TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration M Jung, C Weis, K Chandrasekar, N Wehn Proceedings of the 2013 Workshop on Rapid Simulation and Performance …, 2013 | 51 | 2013 |
| Towards variation-aware system-level power estimation of DRAMs: an empirical approach K Chandrasekar, C Weis, B Akesson, N Wehn, K Goossens Proceedings of the 50th Annual Design Automation Conference, 23, 2013 | 35 | 2013 |
| System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs K Chandrasekar, C Weis, B Akesson, N Wehn, K Goossens Proceedings of the Conference on Design, Automation and Test in Europe (DATE …, 2013 | 35 | 2013 |
| Power/Performance Trade-offs in Real-Time SDRAM Command Scheduling S Goossens, K Chandrasekar, B Akesson, K Goossens IEEE Transactions on Computers, 2015 | 23 | 2015 |
| Run-time power-down strategies for real-time SDRAM memory controllers K Chandrasekar, B Akesson, K Goossens Proceedings of the 49th Annual Design Automation Conference, 988-993, 2012 | 19 | 2012 |
| Memory Controllers for Mixed-Time-Criticality Systems S Goossens, K Chandrasekar, B Akesson, K Goossens Springer, 2016 | 16 | 2016 |
| A Predictor-based Power-Saving Policy for DRAM Memories G Thomas, K Chandrasekar, B Akesson, B Juurlink, K Goossens 15th Euromicro Conference on Digital System Design (DSD), 2012, 2012 | 16 | 2012 |
| High-Level Power Estimation and Optimization of DRAMs K Chandrasekar PhD Dissertation, TU Delft, Delft University of Technology, 2014 | 12 | 2014 |
| Performance Validation of Networks on Chip K Chandrasekar MSc Thesis, TU Delft, Delft University of Technology, 2009 | 4 | 2009 |
Benny ÅkessonSenior Research Fellow, TNO-ESI | Endowed Professor, University of AmsterdamVerified email at tno.nl
