| Edge-centric modulo scheduling for coarse-grained reconfigurable architectures H Park, K Fan, SA Mahlke, T Oh, H Kim, H Kim Proceedings of the 17th international conference on Parallel architectures …, 2008 | 247 | 2008 |
| Application-specific processing on a general-purpose core via transparent instruction set customization N Clark, M Kudlur, H Park, S Mahlke, K Flautner 37th international symposium on microarchitecture (MICRO-37'04), 30-40, 2004 | 239 | 2004 |
| Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications H Park, Y Park, S Mahlke Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009 | 156 | 2009 |
| Modulo graph embedding: Mapping applications onto coarse-grained reconfigurable architectures H Park, K Fan, M Kudlur, S Mahlke Proceedings of the 2006 international conference on Compilers, architecture …, 2006 | 98 | 2006 |
| Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures T Oh, B Egger, H Park, S Mahlke Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages …, 2009 | 67 | 2009 |
| CGRA express: accelerating execution using dynamic operation fusion Y Park, H Park, S Mahlke Proceedings of the 2009 international conference on Compilers, architecture …, 2009 | 66 | 2009 |
| SIMD defragmenter: Efficient ILP realization on data-parallel architectures Y Park, S Seo, H Park, HK Cho, S Mahlke ACM SIGPLAN Notices 47 (4), 363-374, 2012 | 44 | 2012 |
| Cost sensitive modulo scheduling in a loop accelerator synthesis system K Fan, M Kudlur, H Park, S Mahlke 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05 …, 2005 | 43 | 2005 |
| Libra: Tailoring simd execution using heterogeneous hardware and dynamic configurability Y Park, JJK Park, H Park, S Mahlke 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 84-95, 2012 | 36 | 2012 |
| Increasing hardware efficiency with multifunction loop accelerators K Fan, M Kudlur, H Park, S Mahlke Proceedings of the 4th international conference on Hardware/software …, 2006 | 31 | 2006 |
| Allocation of alias registers in a pipelined schedule H Rong, C Wang, P Hyunchul, Y Wu US Patent 9,495,168, 2016 | 11 | 2016 |
| Processor and instruction scheduling method T Oh, H Kim, S Mahlke, HC Park US Patent App. 12/052,356, 2009 | 9 | 2009 |
| Co-designed dynamic language accelerator for a processor C Wang, Y Wu, H Rong, P Hyunchul US Patent 9,542,211, 2017 | 8 | 2017 |
| Dynamic optimization of pipelined software P Hyunchul, H Rong, Y Wu US Patent 9,170,792, 2015 | 8 | 2015 |
| Instruction and logic to monitor loop trip count and remove loop optimizations J Chung, P Hyunchul, H Rong, C Wang, Y Wu US Patent 9,715,388, 2017 | 6 | 2017 |
| Software pipelining at runtime H Rong, P Hyunchul, Y Wu US Patent 9,239,712, 2016 | 6 | 2016 |
| A dataflow-centric approach to design low power control paths in CGRAs H Park, Y Park, S Mahlke 2009 IEEE 7th Symposium on Application Specific Processors, 15-20, 2009 | 6 | 2009 |
| Conjugate code generation for efficient dynamic optimizations H Rong, P Hyunchul, C Wang, Y Wu US Patent 10,268,497, 2019 | 5 | 2019 |
| Compiler-directed synthesis of multifunction loop accelerators K Fan, M Kudlur, H Park, S Mahlke Proc. of the 2005 Workshop on Application Specific Processors, 91-98, 2005 | 5 | 2005 |
| Processor with reconfigurable architecture including a token network simulating processing of processing elements S Heejun, S Kim, P Hyunchul, S Mahlke, P Yongjun US Patent 9,342,478, 2016 | 4 | 2016 |
Scott MahlkeProfessor, Electrical Engineering and Computer Science Dept., University of MichiganVerified email at umich.edu
