| An algorithmic approach for generic parallel adders J Liu, S Zhou, H Zhu, CK Cheng ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 68 | 2003 |
| Optimum prefix adders in a comprehensive area, timing and power design space J Liu, Y Zhu, H Zhu, CK Cheng, J Lillis 2007 Asia and South Pacific Design Automation Conference, 609-615, 2007 | 41 | 2007 |
| On the construction of zero-deficiency parallel prefix circuits with minimum depth H Zhu, CK Cheng, R Graham ACM Transactions on Design Automation of Electronic Systems (TODAES) 11 (2 …, 2006 | 38 | 2006 |
| Constructing zero-deficiency parallel prefix adder of minimum depth H Zhu, CK Cheng, R Graham Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 38 | 2005 |
| Approaching speed-of-light distortionless communication for on-chip interconnect H Zhu, R Shi, CK Cheng, H Chen 2007 Asia and South Pacific Design Automation Conference, 684-689, 2007 | 22 | 2007 |
| Analytical eye-diagram model for on-chip distortionless transmission lines and its application to design space exploration M Hashimoto, J Siriporn, A Tsuchiya, H Zhu, CK Cheng IEICE Transactions on Fundamentals of Electronics, Communications and …, 2008 | 17 | 2008 |
| Predicting and optimizing jitter and eye-opening based on bitonic step response H Zhu, CK Cheng, A Deutsch, G Katopis 2007 IEEE Electrical Performance of Electronic Packaging, 155-158, 2007 | 14 | 2007 |
| Low power passive equalizer optimization using tritonic step response L Zhang, W Yu, H Zhu, A Deutsch, GA Katopis, DM Dreps, E Kuh, ... Proceedings of the 45th annual Design Automation Conference, 570-573, 2008 | 11 | 2008 |
| Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle S Das, H Zhu, KR Bowles, ML Severson US Patent 8,433,944, 2013 | 9 | 2013 |
| Timing-power optimization for mixed-radix Ling adders by integer linear programming Y Zhu, J Liu, H Zhu, CK Cheng 2008 Asia and South Pacific Design Automation Conference, 131-137, 2008 | 8 | 2008 |
| An interconnect-centric approach to cyclic shifter design using fanout splitting and cell order optimization H Zhu, Y Zhu, CK Cheng, DM Harris 2007 Asia and South Pacific Design Automation Conference, 616-621, 2007 | 8 | 2007 |
| Distortion minimization for packaging level interconnects H Zhu, R Shi, H Chen, C Cheng, A Deutsch, G Katopis 2006 IEEE Electrical Performane of Electronic Packaging, 175-178, 2006 | 7 | 2006 |
| Clock skew analysis via vector fitting in frequency domain L Zhang, W Yu, H Zhu, W Zhang, CK Cheng 9th International Symposium on Quality Electronic Design (isqed 2008), 476-479, 2008 | 5 | 2008 |
| Passive compensation for high performance inter-chip communication CC Liu, H Zhu, CK Cheng 2007 25th International Conference on Computer Design, 547-552, 2007 | 5 | 2007 |
| Operand conflict resolution for reduced port general purpose register Y Du, H Shang, H Zhu US Patent 9,632,783, 2017 | 4 | 2017 |
| High performance current-mode differential logic L Zhang, J Liu, H Zhu, CK Cheng, M Hashimoto 2008 Asia and South Pacific Design Automation Conference, 720-725, 2008 | 3 | 2008 |
| High-performance low-power VLSI design H Zhu University of California, San Diego, 2007 | 2 | 2007 |
| On the integer partitioning problem: Examples intuition and beyond H Zhu UCSD Technical Report, 2002 | 1 | 2002 |
| On-Chip Inductance Modeling, Analysis and Simulation H Zhu Class presentation, CSE 245, 2000 | 1 | 2000 |
| An Interconnect-Centric Approach to Cyclic Shifter Design DM Harris, H Zhu, Y Zhu, CK Cheng | | |
