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Saurabh Jain
Saurabh Jain
Research Scientist, Intel Labs
Verified email at intel.com
Title
Cited by
Cited by
Year
A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing
L Lin, S Jain, M Alioto
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 44-46, 2018
362018
Integrated power management for battery-indifferent systems with ultra-wide adaptation down to nW
L Lin, S Jain, M Alioto
IEEE Journal of Solid-State Circuits 55 (4), 967-976, 2019
192019
Dynamically adaptable pipeline for energy-efficient microarchitectures under wide voltage scaling
S Jain, L Lin, M Alioto
IEEE Journal of Solid-State Circuits 53 (2), 632-641, 2017
182017
▒CIM SRAM for signed in-memory broad-purpose computing from DSP to neural processing
S Jain, L Lin, M Alioto
IEEE Journal of Solid-State Circuits 56 (10), 2981-2992, 2021
172021
Embolization of large saccular aneurysms with Gianturco coils.
VR Rao, RK Mandalam, S Joseph, V Satija, VK Gupta, AK Gupta, SK Jain, ...
Radiology 175 (2), 407-410, 1990
141990
Multi-sensor platform with five-order-of-magnitude system power adaptation down to 3.1 nW and sustained operation under moonlight harvesting
L Lin, S Jain, M Alioto
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
132020
Sub-nW microcontroller with dual-mode logic and self-startup for battery-indifferent sensor nodes
L Lin, S Jain, M Alioto
IEEE Journal of Solid-State Circuits 56 (5), 1618-1629, 2020
112020
Broad-purpose in-memory computing for signal monitoring and machine learning workloads
S Jain, L Lin, M Alioto
IEEE Solid-State Circuits Letters 3, 394-397, 2020
112020
Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling
S Jain, L Lin, M Alioto
Cham, Switzerland: Springer, 2020
92020
Design-oriented energy models for wide voltage scaling down to the minimum energy point
S Jain, L Lin, M Alioto
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (12), 3115-3125, 2017
92017
26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage
L Lin, S Jain, M Alioto
2017 IEEE International Solid-State Circuits Conference (ISSCC), 440-441, 2017
72017
Processor energy–performance range extension beyond voltage scaling via drop-in methodologies
S Jain, L Lin, M Alioto
IEEE Journal of Solid-State Circuits 55 (10), 2670-2679, 2020
62020
Automated design of reconfigurable microarchitectures for accelerators under wide-voltage scaling
S Jain, L Lin, M Alioto
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (3), 777-790, 2019
52019
Drop-in energy-performance range extension in microcontrollers beyond VDD scaling
S Jain, L Lin, M Alioto
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 125-128, 2019
52019
A Multi Feature Based Housing Price Prediction for Indian Market Using Machine Learning
R Sawant, S Jain, T Tiwari, Y Jangid, A Gupta
IJCMS 6 (12), 2017
52017
Reconfigurable clock networks for wide voltage scaling
L Lin, S Jain, M Alioto
IEEE Journal of Solid-State Circuits 54 (9), 2622-2631, 2019
42019
Integrated power management and microcontroller for ultra-wide power adaptation down to nW
L Lin, S Jain, M Alioto
2019 Symposium on VLSI Circuits, C178-C179, 2019
42019
A closed-form energy model for VLSI circuits under wide voltage scaling
S Jain, M Alioto
2016 IEEE International Conference on Electronics, Circuits and Systemsá…, 2016
32016
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm
A Gupta, V Konandur, T Salam, S Jain, O Aiello, P Crovetti, M Alioto
2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022
22022
Compute-in-memory using 6t sram for a wide variety of workloads
PK Bharti, S Jain, KR Pillai, SV Sayyaparaju, GS Kalsi, J Mekie, ...
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2963-2967, 2022
12022
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