Deming Chen
Cited by
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Csrnet: Dilated convolutional neural networks for understanding the highly congested scenes
Y Li, X Zhang, D Chen
Proceedings of the IEEE conference on computer vision and pattern …, 2018
Architecture evaluation for power-efficient FPGAs
F Li, D Chen, L He, J Cong
Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field …, 2003
3-D nFPGA: A reconfigurable architecture for 3-D CMOS/nanomaterial hybrid digital circuits
C Dong, D Chen, S Haruehanroengra, W Wang
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (11), 2489-2501, 2007
Springer handbook of automation
SY Nof
Springer Science & Business Media, 2009
FPGA design automation: A survey
D Chen, J Cong, P Pan
Foundations and Trends in Electronic Design Automation 1 (3), 139-169, 2006
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
A Papakonstantinou, K Gururaj, JA Stratton, D Chen, J Cong, WMW Hwu
2009 IEEE 7th Symposium on Application Specific Processors, 35-42, 2009
DAOmap: A depth-optimal area optimization mapping algorithm for FPGA designs
D Chen, J Cong
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
Power modeling and characteristics of field programmable gate arrays
F Li, Y Lin, L He, D Chen, J Cong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005
The sixth visual object tracking vot2018 challenge results
M Kristan, A Leonardis, J Matas, M Felsberg, R Pflugfelder, ...
Proceedings of the European Conference on Computer Vision (ECCV), 0-0, 2018
BLESS: bloom filter-based error correction solution for high-throughput sequencing reads
Y Heo, XL Wu, D Chen, J Ma, WM Hwu
Bioinformatics 30 (10), 1354-1362, 2014
Low-power high-level synthesis for FPGA architectures
D Chen, J Cong, Y Fan
Proceedings of the 2003 international symposium on Low power electronics and …, 2003
Blueshift: Designing processors for timing speculation from the ground up.
B Greskamp, L Wan, UR Karpuzcu, JJ Cook, J Torrellas, D Chen, C Zilles
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
C Dong, D Chen, S Tanachutiwat, W Wang
2007 IEEE/ACM International Conference on Computer-Aided Design, 758-764, 2007
Reconfigurable circuit design with nanomaterials
C Dong, S Chilstedt, D Chen
2009 Design, Automation & Test in Europe Conference & Exhibition, 442-447, 2009
Register binding and port assignment for multiplexer optimization
D Chen, J Cong
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004
An efficient compiler framework for cache bypassing on GPUs
X Xie, Y Liang, G Sun, D Chen
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 516-523, 2013
High-level synthesis: productivity, performance, and software constraints
Y Liang, K Rupnow, Y Li, D Min, MN Do, D Chen
Journal of Electrical and Computer Engineering 2012, 2012
Efficient GPU spatial-temporal multitasking
Y Liang, HP Huynh, K Rupnow, RSM Goh, D Chen
IEEE Transactions on Parallel and Distributed Systems 26 (3), 748-760, 2014
Improving high level synthesis optimization opportunity through polyhedral transformations
W Zuo, Y Liang, P Li, K Rupnow, D Chen, J Cong
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2013
A fast digital predistortion algorithm for radio-frequency power amplifier linearization with loop delay compensation
H Li, DH Kwon, D Chen, Y Chiu
IEEE Journal of selected topics in signal processing 3 (3), 374-383, 2009
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