| Atom: Atomic durability in non-volatile memory through hardware logging A Joshi, V Nagarajan, S Viglas, M Cintra 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 148 | 2017 |
| Efficient persist barriers for multicores A Joshi, V Nagarajan, M Cintra, S Viglas Proceedings of the 48th International Symposium on Microarchitecture, 660-671, 2015 | 148 | 2015 |
| Hermes: A fast, fault-tolerant and linearizable replication protocol A Katsarakis, V Gavrielatos, MRS Katebzadeh, A Joshi, A Dragojevic, ... Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 74 | 2020 |
| Dhtm: Durable hardware transactional memory A Joshi, V Nagarajan, M Cintra, S Viglas 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 71 | 2018 |
| Scale-out ccNUMA: Exploiting skew with strongly consistent caching V Gavrielatos, A Katsarakis, A Joshi, N Oswald, B Grot, V Nagarajan Proceedings of the Thirteenth EuroSys Conference, 1-15, 2018 | 41 | 2018 |
| Lazy release persistency M Dananjaya, V Gavrielatos, A Joshi, V Nagarajan Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 18 | 2020 |
| Kite: Efficient and available release consistency for the datacenter V Gavrielatos, A Katsarakis, V Nagarajan, B Grot, A Joshi Proceedings of the 25th ACM SIGPLAN Symposium on Principles and Practice of …, 2020 | 18 | 2020 |
| Timing variation-aware scheduling and resource binding in high-level synthesis K Mittal, A Joshi, M Mutyam ACM Transactions on Design Automation of Electronic Systems (TODAES) 16 (4 …, 2011 | 11 | 2011 |
| DCA: a DRAM-cache-aware DRAM controller CC Huang, V Nagarajan, A Joshi SC'16: Proceedings of the International Conference for High Performance …, 2016 | 10 | 2016 |
| DHTM: Durable Hardware Transactional Memory. In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). 452–465 A Joshi, V Nagarajan, M Cintra, S Viglas | 8 | 2018 |
| Prevention flow-control for low latency torus networks-on-chip A Joshi, M Mutyam Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on …, 2011 | 6 | 2011 |
| Architectural Support for Atomic Durability in Non-Volatile Memory A Joshi, V Nagarajan, S Viglas, M Cintra 9th Annual Non-Volatile Memories Workshop, 2018 | 1 | 2018 |
| Prevention slot flow‐control mechanism for low latency torus network‐on‐chip A Joshi, P Venkatesh, M Mutyam IET Computers & Digital Techniques 7 (6), 304-316, 2013 | 1 | 2013 |
| Architectural support for persistent memory systems AJ Joshi The University of Edinburgh, 2018 | | 2018 |
| DAPPER: a database-inspired approach to persistent memory M Cintra, A Chatzistergiou, A Joshi, V Nagarajan, SD Viglas The 6th Annual Non-Volatile Memories Workshop (NVMW 2015), 2015 | | 2015 |
| Timing variation-aware scheduling and resource binding in high-level synthesis A Joshi, K Mittal, M Mutyam | | 2011 |
| Hardware support for ACID Transactions in Persistent Memory A Joshi, V Nagarajan, M Cintra, S Viglas | | |
| ICACC 2015 A Unnikrishnan, JK Antony, DD Krishna, J Mathew, J Jose, A Thomas, ... | | |
Vijay NagarajanProfessor, University of UtahVerified email at cs.utah.edu
