Peter Ramm

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Maaike Margrete Visser TakloResearch Manager, SINTEFVerified email at sintef.no
Chris BowerX Display Company, X-Celeprint, Semprius, RTI International, Bell Labs, UNC - Chapel HillVerified email at xdisplay.com
Walter De RaedtimecVerified email at imec.be
A.M. IonescuProfessor of NanoelectronicsVerified email at epfl.ch
Kafil M. RazeebPrincipal Scientist, Team Leader: Advanced Energy Materials, Tyndall National Institute, UCCVerified email at tyndall.ie
Jamila BoudadenFraunhofer EMFTVerified email at emft.fraunhofer.de
Wolfgang Amadeus VitaleR&D Project Leader at ABB SemiconductorsVerified email at ch.abb.com
Aida Todri-SanialFull Professor, TU Eindhoven | Director of Research, CNRSVerified email at tue.nl
Ilja OcketSenior researcher, IMEC and KU LeuvenVerified email at imec.be
Amin EnayatiE&C Anechoic ChambersVerified email at ecac.be
Paul FranzonProfessor of Electrical and Computer Engineering, North Carolina State UniversityVerified email at ncsu.edu
Alan MathewsonUniversity College Cork , NMRC, Tyndall National InstituteVerified email at tyndall.ie
Stefan ZollnerNew Mexico State UniversityVerified email at nmsu.edu
Erik JungFraunhofer IZM, Berlin, GermanyVerified email at izm.fraunhofer.de
Erik Jan MarinissenScientific Director at imecVerified email at imec.be
Nishant MalikUniversity of OsloVerified email at smn.uio.no
Rozalia BeicaCTO at Yole DeveloppementVerified email at yole.fr
John FlakeChemical Engineering, LSUVerified email at lsu.edu
Andrei MullerSwiss Federal Institute Of Intellectual PropertyVerified email at ipi.ch

Peter Ramm

Head of Strategic Projects at Fraunhofer EMFT

Verified email at emft.fraunhofer.de

Si Technology Devices and 3D Integration


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Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits P Garrou, C Bower, P Ramm John Wiley & Sons, 2008	768*	2008
Method of making a three-dimensional integrated circuit P Ramm, R Buchner US Patent 5,563,084, 1996	485	1996
Method of making a three-dimensional integrated circuit P Ramm, R Buchner US Patent 5,877,034, 1999	218	1999
Handbook of Wafer Bonding P Ramm, JJQ Lu, MMV Taklo John Wiley & Sons, 2012	166	2012
Through silicon via technology—processes and reliability for wafer-level 3D system integration P Ramm, MJ Wolf, A Klumpp, R Wieland, B Wunderle, B Michel, H Reichl 2008 58th Electronic Components and Technology Conference, 841-846, 2008	141	2008
Three dimensional metallization for vertically integrated circuits: Invited lecture P Ramm, D Bollmann, R Braun, R Buchner, U Cao-Minh, M Engelhardt, ... Microelectronic Engineering 37, 39-47, 1997	130	1997
Vertical system integration by using inter-chip vias and solid-liquid interdiffusion bonding A Klumpp, R Merkel, P Ramm, J Weber, R Wieland Japanese Journal of Applied Physics 43 (7A), L829, 2004	101	2004
3D integration technology: Status and application development P Ramm, A Klumpp, J Weber, N Lietaer, M Taklo, W De Raedt, T Fritzsch, ... 2010 Proceedings of ESSCIRC, 9-16, 2010	100	2010
Thermo-mechanical reliability of 3D-integrated microstructures in stacked silicon B Wunderle, R Mrossko, O Wittler, E Kaulfersch, P Ramm, B Michel, ... MRS Online Proceedings Library (OPL) 970, 0970-Y02-04, 2006	97	2006
Energy Autonomous Wearable Sensors for Smart Healthcare: A Review AS Dahiya, J Thireau, J Boudaden, S Lal, U Gulzar, Y Zhang, T Gil, ... Journal of The Electrochemical Society 167, 2020	93	2020
3D system integration technologies P Ramm, A Klumpp, R Merkel, J Weber, R Wieland, A Ostmann, J Wolf MRS Online Proceedings Library (OPL) 766, E5. 6, 2003	93	2003
Thermal analysis of vertically integrated circuits MB Kleiner, SA Kuhn, P Ramm, W Weber Proceedings of International Electron Devices Meeting, 487-490, 1995	88	1995
Interchip via technology for vertical system integration P Ramm, D Bonfert, H Gieser, J Haufe, F Iberl, A Klumpp, A Kux, ... Proceedings of the IEEE 2001 International Interconnect Technology …, 2001	80	2001
3D System-on-Chip technologies for More than Moore systems P Ramm, A Klumpp, J Weber, MMV Taklo Microsystem technologies 16, 1051-1055, 2010	77	2010
Method of vertically integrating electric components by means of back contacting P Ramm, A Klumpp US Patent 6,548,391, 2003	64	2003
Method of making a vertical integrated circuit P Ramm, R Buchner US Patent 5,766,984, 1998	64	1998
Face-to-face chip integration with full metal interface H Hübner, O Ehrmann, M Eigner, W Gruber, A Klumpp, R Merkel, ... Advanced Metallization Conference, San Diego 18, 53-58, 2002	63	2002
Technologies for 3D wafer level heterogeneous integration MJ Wolf, P Ramm, A Klumpp, H Reichl 2008 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, 123-126, 2008	60	2008
Handbook of 3D Integration, Volume 3: 3D Process Technology P Garrou, M Koyanagi, P Ramm John Wiley & Sons, 2014	58	2014
Method of vertically integrating microelectronic systems P Ramm US Patent 5,851,894, 1998	57	1998

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