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Stefan Holst
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Cited by
Year
Adaptive debug and diagnosis without fault dictionaries
S Holst, HJ Wunderlich
Journal of Electronic Testing 25, 259-268, 2009
1442009
Restrict encoding for mixed-mode BIST
AW Hakmi, S Holst, HJ Wunderlich, J Schlöffel, F Hapke, A Glowatz
2009 27th IEEE VLSI Test Symposium, 179-184, 2009
562009
High-throughput logic timing simulation on GPGPUs
S Holst, ME Imhof, HJ Wunderlich
ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (3 …, 2015
352015
GPU-accelerated simulation of small delay faults
E Schneider, MA Kochte, S Holst, X Wen, HJ Wunderlich
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
332016
A diagnosis algorithm for extreme space compaction
S Holst, HJ Wunderlich
2009 Design, Automation & Test in Europe Conference & Exhibition, 1355-1360, 2009
292009
GPU-accelerated small delay fault simulation
E Schneider, S Holst, MA Kochte, X Wen, HJ Wunderlich
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
262015
Scan test power simulation on GPGPUs
S Holst, E Schneider, HJ Wunderlich
2012 IEEE 21st Asian Test Symposium, 155-160, 2012
222012
Generalized fault modeling for logic diagnosis
HJ Wunderlich, S Holst
Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian …, 2010
202010
Structural test for graceful degradation of NoC switches
A Dalirsani, S Holst, M Elm, HJ Wunderlich
2011 Sixteenth IEEE European Test Symposium, 183-188, 2011
192011
Formal test point insertion for region-based low-capture-power compact at-speed scan test
S Eggersglüß, S Holst, D Tille, K Miyase, X Wen
2016 IEEE 25th Asian Test Symposium (ATS), 173-178, 2016
162016
Soft-error tolerant TCAMs for high-reliability packet classifications
I Syafalni, T Sasao, X Wen, S Holst, K Miyase
2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 471-474, 2014
142014
Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures
C Braun, S Holst, HJ Wunderlich, JM Castillo, J Gross
2012 IEEE 30th International Conference on Computer Design (ICCD), 207-212, 2012
112012
Logic/clock-path-aware at-speed scan test generation for avoiding false capture failures and reducing clock stretch
K Asada, X Wen, S Holst, K Miyase, S Kajihara, MA Kochte, E Schneider, ...
2015 IEEE 24th Asian Test Symposium (ATS), 103-108, 2015
102015
Data-parallel simulation for fast and accurate timing validation of CMOS circuits
E Schneider, S Holst, X Wen, HJ Wunderlich
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 17-23, 2014
102014
Variation-aware small delay fault diagnosis on compressed test responses
S Holst, E Schneider, MA Kochte, X Wen, HJ Wunderlich
2019 IEEE International Test Conference (ITC), 1-10, 2019
92019
A fault-tolerant MPSoC for CubeSats
CM Fuchs, P Chou, X Wen, NM Murillo, G Furano, S Holst, A Tavoularis, ...
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2019
92019
STAHL: A novel scan-test-aware hardened latch design
R Ma, S Holst, X Wen, A Yan, H Xu
2019 IEEE European Test Symposium (ETS), 1-6, 2019
82019
Analysis and mitigation or IR-Drop induced scan shift-errors
S Holst, E Schneider, K Kawagoe, MA Kochte, K Miyase, HJ Wunderlich, ...
2017 IEEE International Test Conference (ITC), 1-8, 2017
82017
The impact of production defects on the soft-error tolerance of hardened latches
S Holst, R Ma, X Wen
2018 IEEE 23rd European Test Symposium (ETS), 1-6, 2018
72018
Test encoding for extreme response compaction
MA Kochte, S Holst, M Elm, HJ Wunderlich
2009 14th IEEE European Test Symposium, 155-160, 2009
72009
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