Sai Manoj P D
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Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification
H Sayadi, N Patel, SM P D, A Sasan, S Rafatirad, H Homayoun
Design Automation Conference, 1, 2018
Reliable 3-D clock-tree synthesis considering nonlinear capacitive TSV model with electrical–thermal–mechanical coupling
MPD Sai, H Yu, Y Shang, CS Tan, SK Lim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
Customized machine learning-based hardware-assisted malware detection in embedded devices
H Sayadi, HM Makrani, O Randive, SM PD, S Rafatirad, H Homayoun
2018 17th IEEE International Conference On Trust, Security And Privacy In …, 2018
2smart: A two-stage machine learning-based approach for run-time specialized hardware-assisted malware detection
H Sayadi, HM Makrani, SMP Dinakarrao, T Mohsenin, A Sasan, ...
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 728-733, 2019
Adversarial attack on microarchitectural events based malware detectors
SMP Dinakarrao, S Amberkar, S Bhat, A Dhavlle, H Sayadi, A Sasan, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
Machine learning for power, energy, and thermal management on multicore processors: A survey
S Pagani, PDS Manoj, A Jantsch, J Henkel
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
Neural network based ECG anomaly detection on FPGA and trade-off analysis
M Wess, PDS Manoj, A Jantsch
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
A scalable network-on-chip microprocessor with 2.5 D integrated memory and accelerator
SM PD, J Lin, S Zhu, Y Yin, X Liu, X Huang, C Song, W Zhang, M Yan, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (6), 1432-1443, 2017
Comprehensive Assessment of Run-Time Hardware-Supported Malware Detection Using General and Ensemble Learning
H Sayadi, SM P D, A Houmansadr, S Rafatirad, Homayoun
ACM International Conference on Computing Frontiers, 2018
Lightweight node-level malware detection and network-level malware confinement in iot networks
SMP Dinakarrao, H Sayadi, HM Makrani, C Nowzari, S Rafatirad, ...
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 776-781, 2019
Security and complexity analysis of lut-based obfuscation: From blueprint to reality
G Kolhe, HM Kamali, M Naicker, TD Sheaves, H Mahmoodi, PDS Manoj, ...
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
Weighted quantization-regularization in DNNs for weight memory minimization toward HW implementation
M Wess, SMP Dinakarrao, A Jantsch
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
Advances and Throwbacks in Hardware-Assisted Security
F Brasser, L Davi, A Dhavlle, T Frassetto, SMP Dinakarrao, S Rafatirad, ...
International Conference on Compilers, Architectures and Synthesis for …, 2018
On custom lut-based obfuscation
G Kolhe, SM PD, S Rafatirad, H Mahmoodi, A Sasan, H Homayoun
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 477-482, 2019
A Q-learning based self-adaptive I/O communication for 2.5 D integrated many-core microprocessor and memory
SM PD, H Yu, H Huang, D Xu
IEEE Transactions on Computers 65 (4), 1185-1196, 2015
3D many-core microprocessor power management by space-time multiplexing based demand-supply matching
SM PD, H Yu, K Wang
IEEE Transactions on Computers 64 (11), 3022-3036, 2015
A comprehensive memory analysis of data intensive workloads on server class architecture
HM Makrani, H Sayadi, SMP Dinakarra, S Rafatirad, H Homayoun
Proceedings of the International Symposium on Memory Systems, 19-30, 2018
A thermal resilient integration of many-core microprocessors and main memory by 2.5 D TSI I/Os
SS Wu, K Wang, MPD Sai, TY Ho, M Yu, H Yu
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
Memristors' potential for multi-bit storage and pattern learning
N Taherinejad, PDS Manoj, A Jantsch
2015 IEEE European Modelling Symposium (EMS), 450-455, 2015
High-speed and low-power 2.5 DI/O circuits for memory-logic-integration by through-silicon interposer
J Wang, S Ma, PDS Manoj, M Yu, R Weerasekera, H Yu
2013 IEEE International 3D Systems Integration Conference (3DIC), 1-4, 2013
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