Follow
jinshan yue
Title
Cited by
Cited by
Year
Sticker: A 0.41-62.1 TOPS/W 8Bit neural network processor with multi-sparsity compatible convolution arrays and online tuning acceleration for fully connected layers
Z Yuan, J Yue, H Yang, Z Wang, J Li, Y Yang, Q Guo, X Li, MF Chang, ...
2018 IEEE symposium on VLSI circuits, 33-34, 2018
902018
14.3 a 65nm computing-in-memory-based cnn processor with 2.9-to-35.8 tops/w system energy efficiency using dynamic-sparsity performance-scaling architecture and energy …
J Yue, Z Yuan, X Feng, Y He, Z Zhang, X Si, R Liu, MF Chang, X Li, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 234-236, 2020
822020
15.2 A 2.75-to-75.9 TOPS/W computing-in-memory NN processor supporting set-associate block-wise zero skipping and ping-pong CIM with simultaneous computation and weight updating
J Yue, X Feng, Y He, Y Huang, Y Wang, Z Yuan, M Zhan, J Liu, JW Su, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 238-240, 2021
442021
7.5 A 65nm 0.39-to-140.3 TOPS/W 1-to-12b unified neural network processor using block-circulant-enabled transpose-domain acceleration with 8.1× higher TOPS/mm 2 and 6T HBST …
J Yue, R Liu, W Sun, Z Yuan, Z Wang, YN Tu, YJ Chen, A Ren, Y Wang, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 138-140, 2019
362019
STICKER: An energy-efficient multi-sparsity compatible accelerator for convolutional neural networks in 65-nm CMOS
Z Yuan, Y Liu, J Yue, Y Yang, J Wang, X Feng, J Zhao, X Li, H Yang
IEEE Journal of Solid-State Circuits 55 (2), 465-477, 2019
352019
Data backup optimization for nonvolatile SRAM in energy harvesting sensor nodes
Y Liu, J Yue, H Li, Q Zhao, M Zhao, CJ Xue, G Sun, MF Chang, H Yang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
192017
A 3.77 TOPS/W convolutional neural network processor with priority-driven kernel optimization
J Yue, Y Liu, Z Yuan, Z Wang, Q Guo, J Li, C Yang, H Yang
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (2), 277-281, 2018
162018
Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead
H Li, Y Liu, C Fu, CJ Xue, D Xiang, J Yue, J Li, D Zhang, J Hu, H Yang
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
132016
14.2 A 65nm 24.7 µJ/Frame 12.3 mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width …
Z Yuan, Y Yang, J Yue, R Liu, X Feng, Z Lin, X Wu, X Li, H Yang, Y Liu
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 232-234, 2020
122020
PATH: Performance-aware task scheduling for energy-harvesting nonvolatile processors
J Li, Y Liu, H Li, Z Yuan, C Fu, J Yue, X Feng, CJ Xue, J Hu, H Yang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (9 …, 2018
112018
CORAL: coarse-grained reconfigurable architecture for convolutional neural networks
Z Yuan, Y Liu, J Yue, J Li, H Yang
2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017
112017
A sparse-adaptive CNN processor with area/performance balanced N-way set-associate PE arrays assisted by a collision-aware scheduler
Z Yuan, J Wang, Y Yang, J Yue, Z Wang, X Feng, Y Wang, X Li, H Yang, ...
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 61-64, 2019
82019
High pe utilization cnn accelerator with channel fusion supporting pattern-compressed sparse neural networks
J Wang, S Yu, J Yue, Z Yuan, Z Yuan, H Yang, X Li, Y Liu
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
72020
AERIS: Area/Energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip
J Yue, Y Liu, F Su, S Li, Z Yuan, Z Wang, W Sun, X Li, H Yang
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
52019
STICKER-T: An energy-efficient neural network processor using block-circulant algorithm and unified frequency-domain acceleration
J Yue, Y Liu, R Liu, W Sun, Z Yuan, YN Tu, YJ Chen, A Ren, Y Wang, ...
IEEE Journal of Solid-State Circuits 56 (6), 1936-1948, 2020
42020
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse
J Yue, Y Liu, Z Yuan, X Feng, Y He, W Sun, Z Zhang, X Si, R Liu, Z Wang, ...
IEEE Journal of Solid-State Circuits, 2022
32022
Trending IC design directions in 2022
CH Chan, L Cheng, W Deng, P Feng, L Geng, M Huang, H Jia, L Jie, ...
Journal of Semiconductors 43, 071401-1-071401-47, 2022
32022
Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems
Y Huang, Y He, J Yue, H Yang, Y Liu
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (2), 518-529, 2021
22021
Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules
Y He, J Yue, Y Liu, H Yang
2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 813-818, 2021
22021
High Area/Energy Efficiency RRAM CNN Accelerator With Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning
S Yu, Y Liu, L Zhang, J Wang, J Yue, Z Yuan, X Li, H Yang
arXiv preprint arXiv:2010.06156, 2020
22020
The system can't perform the operation now. Try again later.
Articles 1–20