| 14.3 A 65nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy … J Yue, Z Yuan, X Feng, Y He, Z Zhang, X Si, R Liu, MF Chang, X Li, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 234-236, 2020 | 125 | 2020 |
| 15.2 A 2.75-to-75.9 TOPS/W computing-in-memory NN processor supporting set-associate block-wise zero skipping and ping-pong CIM with simultaneous computation and weight updating J Yue, X Feng, Y He, Y Huang, Y Wang, Z Yuan, M Zhan, J Liu, JW Su, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 238-240, 2021 | 114 | 2021 |
| Sticker: A 0.41-62.1 TOPS/W 8Bit neural network processor with multi-sparsity compatible convolution arrays and online tuning acceleration for fully connected layers Z Yuan, J Yue, H Yang, Z Wang, J Li, Y Yang, Q Guo, X Li, MF Chang, ... 2018 IEEE symposium on VLSI circuits, 33-34, 2018 | 111 | 2018 |
| STICKER: An energy-efficient multi-sparsity compatible accelerator for convolutional neural networks in 65-nm CMOS Z Yuan, Y Liu, J Yue, Y Yang, J Wang, X Feng, J Zhao, X Li, H Yang IEEE Journal of Solid-State Circuits 55 (2), 465-477, 2019 | 69 | 2019 |
| 7.5 A 65nm 0.39-to-140.3 TOPS/W 1-to-12b unified neural network processor using block-circulant-enabled transpose-domain acceleration with 8.1× higher TOPS/mm 2 and 6T HBST … J Yue, R Liu, W Sun, Z Yuan, Z Wang, YN Tu, YJ Chen, A Ren, Y Wang, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 138-140, 2019 | 46 | 2019 |
| 14.2 A 65nm 24.7 µJ/Frame 12.3 mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width … Z Yuan, Y Yang, J Yue, R Liu, X Feng, Z Lin, X Wu, X Li, H Yang, Y Liu 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 232-234, 2020 | 31 | 2020 |
| A 3.77 TOPS/W convolutional neural network processor with priority-driven kernel optimization J Yue, Y Liu, Z Yuan, Z Wang, Q Guo, J Li, C Yang, H Yang IEEE Transactions on Circuits and Systems II: Express Briefs 66 (2), 277-281, 2018 | 26 | 2018 |
| STICKER-IM: A 65 nm computing-in-memory NN processor using block-wise sparsity optimization and inter/intra-macro data reuse J Yue, Y Liu, Z Yuan, X Feng, Y He, W Sun, Z Zhang, X Si, R Liu, Z Wang, ... IEEE Journal of Solid-State Circuits 57 (8), 2560-2573, 2022 | 24 | 2022 |
| Data backup optimization for nonvolatile SRAM in energy harvesting sensor nodes Y Liu, J Yue, H Li, Q Zhao, M Zhao, CJ Xue, G Sun, MF Chang, H Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 22 | 2017 |
| A 28nm 16.9-300TOPS/W computing-in-memory processor supporting floating-point NN inference/training with intensive-CIM sparse-digital architecture J Yue, C He, Z Wang, Z Cong, Y He, M Zhou, W Sun, X Li, C Dou, F Zhang, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 1-3, 2023 | 21 | 2023 |
| Trending IC design directions in 2022 CH Chan, L Cheng, W Deng, P Feng, L Geng, M Huang, H Jia, L Jie, ... Journal of Semiconductors 43 (7), 071401, 2022 | 20 | 2022 |
| High pe utilization CNN accelerator with channel fusion supporting pattern-compressed sparse neural networks J Wang, S Yu, J Yue, Z Yuan, Z Yuan, H Yang, X Li, Y Liu 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 16 | 2020 |
| CORAL: coarse-grained reconfigurable architecture for convolutional neural networks Z Yuan, Y Liu, J Yue, J Li, H Yang 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 14 | 2017 |
| A sparse-adaptive CNN processor with area/performance balanced N-way set-associate PE arrays assisted by a collision-aware scheduler Z Yuan, J Wang, Y Yang, J Yue, Z Wang, X Feng, Y Wang, X Li, H Yang, ... 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 61-64, 2019 | 13 | 2019 |
| PATH: Performance-aware task scheduling for energy-harvesting nonvolatile processors J Li, Y Liu, H Li, Z Yuan, C Fu, J Yue, X Feng, CJ Xue, J Hu, H Yang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (9 …, 2018 | 13 | 2018 |
| Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead H Li, Y Liu, C Fu, CJ Xue, D Xiang, J Yue, J Li, D Zhang, J Hu, H Yang Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 13 | 2016 |
| An RRAM-based digital computing-in-memory macro with dynamic voltage sense amplifier and sparse-aware approximate adder tree Y He, J Yue, X Feng, Y Huang, H Jia, J Wang, L Zhang, W Sun, H Yang, ... IEEE Transactions on Circuits and Systems II: Express Briefs 70 (2), 416-420, 2022 | 10 | 2022 |
| 7.3 a 28nm 38-to-102-TOPS/W 8b multiply-less approximate digital SRAM compute-in-memory macro for neural-network inference Y He, H Diao, C Tang, W Jia, X Tang, Y Wang, J Yue, X Li, H Yang, H Jia, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 130-132, 2023 | 8 | 2023 |
| AERIS: Area/Energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip J Yue, Y Liu, F Su, S Li, Z Yuan, Z Wang, W Sun, X Li, H Yang Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 8 | 2019 |
| A 28-nm RRAM computing-in-memory macro using weighted hybrid 2T1R cell array and reference subtracting sense amplifier for AI edge inference W Ye, L Wang, Z Zhou, J An, W Li, H Gao, Z Li, J Yue, H Hu, X Xu, J Yang, ... IEEE Journal of Solid-State Circuits, 2023 | 7 | 2023 |
Huazhong YangProfessor of Electronics Engineering, Tsinghua UniversityVerified email at tsinghua.edu.cn
