| CMOS implementation of a fast 4-2 compressor for parallel accumulations A Fathi, S Azizian, K Hadidi, A Khoei, A Chegeni 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 1476-1479, 2012 | 19 | 2012 |
| Improved genetic algorithm-based optimization of fuzzy logic controllers A Chegeni, A Khoei, K Hadidi First Joint Congress on Fuzzy and Intelligent Systems, Ferdowsi University …, 2007 | 8 | 2007 |
| A histogram-based background interstage error estimation and implementation method in pipelined ADCs A Chegeni, K Hadidi, A Khoei IEEE Transactions on Circuits and Systems II: Express Briefs 65 (11), 1519-1523, 2017 | 3 | 2017 |
| Input dependent clock jitter in high speed and high resolution ADCs A Chegeni, R Shayanfar, K Hadidi, A Khoei 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2997-3000, 2012 | 2 | 2012 |
| Design of a High Speed, Low Latency and Low Power Consumption DRAM Using two-transistor Cell Structure A Chegeni, K Hadidi, A Khoei 2007 14th IEEE International Conference on Electronics, Circuits and Systems …, 2007 | 1 | 2007 |
| Pre-charge solution for low-power, area-efficient SAR ADC S Sarafi, AKB Aain, JA Bargoshadi, A Chegini IEICE Electronics Express, 12.20150546, 2015 | | 2015 |
Abdollah KhoeiProfessor of Electrical EngineeringVerified email at urmia.ac.ir
Abdollah KhoeiProfessor of Electrical EngineeringVerified email at urmia.ac.ir