Charles Augustine
Charles Augustine
Intel, Georgia Tech, Purdue, NXP, Philips, Texas Instruments
Verified email at - Homepage
Cited by
Cited by
Event-driven random back-propagation: Enabling neuromorphic deep learning machines
EO Neftci, C Augustine, S Paul, G Detorakis
Frontiers in neuroscience 11, 324, 2017
Spin-based neuron model with domain-wall magnets as synapse
M Sharad, C Augustine, G Panagopoulos, K Roy
IEEE Transactions on Nanotechnology 11 (4), 843-853, 2012
H Naeimi, C Augustine, A Raychowdhury, SL Lu, J Tschanz
intel technology journal 17 (1), 2013
KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells
X Fong, SK Gupta, NN Mojumder, SH Choday, C Augustine, K Roy
2011 International Conference on Simulation of Semiconductor Processes and …, 2011
TapeCache: A high density, energy efficient cache based on domain wall memory
R Venkatesan, V Kozhikkottu, C Augustine, A Raychowdhury, K Roy, ...
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
Low-power functionality enhanced computation architecture using spin-based devices
C Augustine, G Panagopoulos, B Behin-Aein, S Srinivasan, A Sarkar, ...
2011 IEEE/ACM International Symposium on Nanoscale Architectures, 129-136, 2011
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement
J Li, C Augustine, S Salahuddin, K Roy
Proceedings of the 45th annual Design Automation Conference, 278-283, 2008
Physics-based SPICE-compatible compact model for simulating hybrid MTJ/CMOS circuits
GD Panagopoulos, C Augustine, K Roy
IEEE Transactions on Electron Devices 60 (9), 2808-2814, 2013
Detecting keywords in audio using a spiking neural network
M Khellah, O Arad, B Ravindran, S Paul, C Augustine, BU Pedroni
US Patent 10,403,266, 2019
Postsilicon voltage guard-band reduction in a 22 nm graphics execution core using adaptive voltage scaling and dynamic power gating
M Cho, ST Kim, C Tokunaga, C Augustine, JP Kulkarni, K Ravichandran, ...
IEEE Journal of Solid-State Circuits 52 (1), 50-63, 2016
Enabling wide autonomous DVFS in a 22 nm graphics execution core using a digitally controlled fully integrated voltage regulator
ST Kim, YC Shih, K Mazumdar, R Jain, JF Ryan, C Tokunaga, ...
IEEE Journal of Solid-State Circuits 51 (1), 18-30, 2015
Spin-transfer torque MRAMs for low power memories: Perspective and prospective
C Augustine, NN Mojumder, X Fong, SH Choday, SP Park, K Roy
IEEE Sensors Journal 12 (4), 756-766, 2011
SPICE models for magnetic tunnel junctions based on monodomain approximation
X Fong, SH Choday, P Georgios, C Augustine, K Roy
NanoHub, 2013
Resistive memory write operation with merged reset
H Naeimi, SLL Lu, C Augustine
US Patent 9,520,192, 2016
Numerical analysis of domain wall propagation for dense memory arrays
C Augustine, A Raychowdhury, B Behin-Aein, S Srinivasan, J Tschanz, ...
2011 International Electron Devices Meeting, 17.6. 1-17.6. 4, 2011
Write operations in spin transfer torque memory
H Naeimi, SLL Lu, C Augustine
US Patent 9,299,412, 2016
Proposal for neuromorphic hardware using spin devices
M Sharad, C Augustine, G Panagopoulos, K Roy
arXiv preprint arXiv:1206.3227, 2012
Modeling of dielectric breakdown-induced time-dependent STT-MRAM performance degradation
G Panagopoulos, C Augustine, K Roy
69th Device Research Conference, 125-126, 2011
Numerical analysis of typical STT-MTJ stacks for 1T-1R memory arrays
C Augustine, A Raychowdhury, D Somasekhar, J Tschanz, K Roy, VK De
2010 International Electron Devices Meeting, 22.7. 1-22.7. 4, 2010
Effect of quantum confinement on spin transport and magnetization dynamics in dual barrier spin transfer torque magnetic tunnel junctions
NN Mojumder, C Augustine, DE Nikonov, K Roy
Journal of Applied Physics 108 (10), 2010
The system can't perform the operation now. Try again later.
Articles 1–20