| Handbook of floating-point arithmetic JM Muller, N Brisebarre, F De Dinechin, CP Jeannerod, V Lefevre, ... Birkhäuser, 2018 | 850 | 2018 |
| Designing custom arithmetic data paths with FloPoCo F De Dinechin, B Pasca IEEE Design & Test of Computers 28 (4), 18-27, 2011 | 387 | 2011 |
| Multipartite table methods F De Dinechin, A Tisserand IEEE Transactions on Computers 54 (3), 319-330, 2005 | 228 | 2005 |
| Large multipliers with fewer DSP blocks F de Dinechin, B Pasca 2009 International Conference on Field Programmable Logic and Applications …, 2009 | 140* | 2009 |
| Certifying the floating-point implementation of an elementary function using Gappa F De Dinechin, C Lauter, G Melquiond IEEE Transactions on Computers 60 (2), 242-253, 2010 | 131 | 2010 |
| Table-based polynomials for fast hardware function evaluation J Detrey, F de Dinechin 2005 IEEE International Conference on Application-Specific Systems …, 2005 | 115 | 2005 |
| An FPGA-specific approach to floating-point accumulation and sum-of-products F De Dinechin, B Pasca, O Cret, R Tudoran 2008 International Conference on Field-Programmable Technology, 33-40, 2008 | 107 | 2008 |
| Assisted verification of elementary functions using Gappa F De Dinechin, CQ Lauter, G Melquiond Proceedings of the 2006 ACM symposium on Applied computing, 1318-1322, 2006 | 103 | 2006 |
| Some improvements on multipartite table methods F de Dinechin, A Tisserand Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, 128-135, 2001 | 92 | 2001 |
| Multipliers for floating-point double precision and beyond on FPGAs S Banescu, F De Dinechin, B Pasca, R Tudoran ACM SIGARCH Computer Architecture News 38 (4), 73-79, 2011 | 90 | 2011 |
| Parameterized floating-point logarithm and exponential functions for FPGAs J Detrey, F de Dinechin Microprocessors and Microsystems 31 (8), 537-545, 2007 | 88 | 2007 |
| Posits: the good, the bad and the ugly F De Dinechin, L Forget, JM Muller, Y Uguen Proceedings of the Conference for Next Generation Arithmetic 2019, 1-10, 2019 | 81 | 2019 |
| Generating high-performance custom floating-point pipelines F De Dinechin, C Klein, B Pasca 2009 International Conference on Field Programmable Logic and Applications …, 2009 | 81 | 2009 |
| When FPGAs are better at floating-point than microprocessors. F De Dinechin, J Detrey, O Cret, R Tudoran FPGA 8, 260, 2008 | 70 | 2008 |
| A VHDL library of LNS operators J Detrey, F de Dinechin The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003 …, 2003 | 67 | 2003 |
| Automatic generation of polynomial-based hardware architectures for function evaluation F De Dinechin, M Joldes, B Pasca ASAP 2010-21st IEEE International Conference on Application-specific Systems …, 2010 | 64 | 2010 |
| Return of the hardware floating-point elementary function J Detrey, F De Dinechin, X Pujol 18th IEEE Symposium on Computer Arithmetic (ARITH'07), 161-168, 2007 | 64 | 2007 |
| A tool for unbiased comparison between logarithmic and floating-point arithmetic J Detrey, F De Dinechin The Journal of VLSI Signal Processing Systems for Signal, Image, and Video …, 2007 | 63 | 2007 |
| A parameterized floating-point exponential function for FPGAs J Detrey, F de Dinechin Proceedings. 2005 IEEE International Conference on Field-Programmable …, 2005 | 59 | 2005 |
| Fast and correctly rounded logarithms in double-precision F De Dinechin, C Lauter, JM Muller RAIRO - Theoretical Informatics and Applications 41 (01), 85-102, 2007 | 57 | 2007 |
jean-michel mullerCNRS, Ecole Normale Supérieure de Lyon, INRIA, Université de LyonVerified email at ens-lyon.fr
