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Heng Wu
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Chloride Molecular Doping Technique on 2D Materials: WS2 and MoS2
L Yang, K Majumdar, H Liu, Y Du, H Wu, M Hatzistergos, PY Hung, ...
Nano letters 14 (11), 6275-6280, 2014
7702014
Vertical field-effect transistor with uniform bottom spacer
J Li, K Cheng, P Xu, H Wu
US Patent App. 15/830,665, 2019
1952019
20–80nm channel length InGaAs gate-all-around nanowire MOSFETs with EOT= 1.2 nm and lowest SS= 63mV/dec
JJ Gu, XW Wang, H Wu, J Shao, AT Neal, MJ Manfra, RG Gordon, PD Ye
2012 International Electron Devices Meeting, 27.6. 1-27.6. 4, 2012
1102012
High-performance MoS2field-effect transistors enabled by chloride doping: Record low contact resistance (0.5 kΩ·µm) and record high drain current (460 µA/µm)
L Yang, K Majumdar, Y Du, H Liu, H Wu, M Hatzistergos, PY Hung, ...
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014
872014
Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications
J Zhang, J Frougier, A Greene, X Miao, L Yu, R Vega, P Montanini, ...
2019 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2019
692019
Size-Dependent-Transport Study of Gate-All-Around Nanowire MOSFETs: Impact of Quantum Confinement and Volume Inversion
JJ Gu, H Wu, Y Liu, AT Neal, RG Gordon, DY Peide
IEEE electron device letters 33 (7), 967-969, 2012
592012
High-performance InAlN/GaN MOSHEMTs enabled by atomic layer epitaxy MgCaO as gate dielectric
H Zhou, X Lou, NJ Conrad, M Si, H Wu, S Alghamdi, S Guo, RG Gordon, ...
IEEE Electron Device Letters 37 (5), 556-559, 2016
582016
First demonstration of Ge nanowire CMOS circuits: Lowest SS of 64 mV/dec, highest gmax of 1057 uS/um in Ge nFETs and highest maximum voltage gain of 54 V/V in Ge CMOS inverters
H Wu, W Wu, M Si, PD Ye
2015 IEEE International Electron Devices Meeting (IEDM), 2015
542015
A 14 nm embedded stt-mram cmos technology
D Edelstein, M Rizzolo, D Sil, A Dutta, J DeBrosse, M Wordeman, A Arceo, ...
2020 IEEE International Electron Devices Meeting (IEDM), 11.5. 1-11.5. 4, 2020
482020
First experimental demonstration of Ge CMOS circuits
H Wu, N Conrad, W Luo, DY Peide
2014 IEEE International Electron Devices Meeting, 9.3. 1-9.3. 4, 2014
482014
Parasitic resistance reduction strategies for advanced CMOS FinFETs beyond 7nm
H Wu, O Gluschenkov, G Tsutsui, C Niu, K Brew, C Durfee, C Prindle, ...
2018 IEEE International Electron Devices Meeting (IEDM), 35.4. 1-35.4. 4, 2018
432018
First experimental demonstration of Ge 3D FinFET CMOS circuits
H Wu, W Luo, H Zhou, M Si, J Zhang, DY Peide
2015 Symposium on VLSI Technology (VLSI Technology), T58-T59, 2015
412015
Germanium nMOSFETs with recessed channel and S/D: Contact, scalability, interface, and drain current exceeding 1 A/mm
H Wu, M Si, L Dong, J Gu, J Zhang, DY Peide
IEEE Transactions on Electron Devices 62 (5), 1419-1426, 2015
372015
Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices
H Jagannathan, B Anderson, CW Sohn, G Tsutsui, J Strane, R Xie, S Fan, ...
2021 IEEE International Electron Devices Meeting (IEDM), 26.1. 1-26.1. 4, 2021
332021
Substrate and layout engineering to suppress self-heating in floating body transistors
MAA SH Shin, S-H Kim, S Kim, H Wu, PD Ye
Electron Devices Meeting (IEDM), 2016 IEEE International, 15.7. 1-15.7. 4, 2016
32*2016
Fully Depleted Ge CMOS Devices and Logic Circuits on Si
H Wu, DY Peide
IEEE Transactions on Electron Devices 63 (8), 3028-3035, 2016
292016
Demonstration of Ge Nanowire CMOS Devices and Circuits for Ultimate Scaling
H Wu, W Wu, M Si, PD Ye
IEEE Transactions on Electron Devices 63 (8), 3049-3057, 2016
282016
Ge CMOS: Breakthroughs of nFETs (Imax=714 mA/mm, gmax=590 mS/mm) by recessed channel and S/D
H Wu, M Si, L Dong, J Zhang, DY Peide
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014
282014
Formation of a partial air-gap spacer
CH Lee, K Cheng, H Wu, P Xu
US Patent 11,011,617, 2021
262021
Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap
K Cheng, Z Liu, S Naczas, H Wu, P Xu
US Patent 10,056,289, 2018
242018
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