Siva Satyendra Sahoo
Siva Satyendra Sahoo
Postdoctoral Researcher, Chair for Processor Design, Technische Universität Dresden
Verified email at tu-dresden.de - Homepage
Title
Cited by
Cited by
Year
Cross-layer fault-tolerant design of real-time systems
SS Sahoo, B Veeravalli, A Kumar
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016 …, 2016
162016
Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faults
SS Sahoo, A Kumar, B Veeravalli
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016 …, 2016
142016
Lifetime-aware design methodology for dynamic partially reconfigurable systems
SS Sahoo, TDA Nguyen, B Veeravalli, A Kumar
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 393-398, 2018
62018
A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems
SS Sahoo, B Veeravalli, A Kumar
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
52019
Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures
S Ullah, H Schmidl, SS Sahoo, S Rehman, A Kumar
IEEE Transactions on Computers, 2020
42020
Discern: Distilling standard-cells for emerging reconfigurable nanotechnologies
S Rai, M Raitza, SS Sahoo, A Kumar
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 674-677, 2020
42020
Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems
SS Sahoo, TDA Nguyen, B Veeravalli, A Kumar
Integration 67, 95-107, 2019
42019
CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems
SS Sahoo, B Veeravalli, A Kumar
VLSI Design and 2018 17th International Conference on Embedded Systems …, 2018
42018
ExPAN (N) D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems
S Nambi, S Ullah, A Lohana, SS Sahoo, F Merchant, A Kumar
arXiv preprint arXiv:2010.12869, 2020
22020
Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems
SS Sahoo, B Veeravalli, A Kumar
2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2020
22020
CL (R) Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems
SS Sahoo, B Veeravalli, A Kumar
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
22020
QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning
SS Sahoo, TDA Nguyen, B Veeravalli, A Kumar
2018 International Conference on Field-Programmable Technology (FPT), 230-233, 2018
22018
Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper
SS Sahoo, B Ranjbar, A Kumar
Journal of Low Power Electronics and Applications 11 (1), 7, 2021
2021
ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems
AR Baranwal, S Ullah, SS Sahoo, A Kumar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
2020
A CROSS-LAYER RELIABILITY-INTEGRATED SYSTEM-LEVEL DESIGN METHODOLOGY FOR HETEROGENEOUS MULTIPROCESSOR SOC-BASED EMBEDDED SYSTEMS
SS SAHOO
2019
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