| High density chip carrier with integrated passive devices MP Chudzik, RH Dennard, R Divakaruni, BK Furman, R Jammy, ... US Patent 7,030,481, 2006 | 374 | 2006 |
| High density chip carrier with integrated passive devices MP Chudzik, RH Dennard, R Divakaruni, BK Furman, R Jammy, ... US Patent 6,962,872, 2005 | 332 | 2005 |
| A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates S Zafar, Y Kim, V Narayanan, C Cabral, V Paruchuri, B Doris, J Stathis, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 23-25, 2006 | 285 | 2006 |
| Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric S Siddiqui, MP Chudzik, CJ Radens US Patent 8,373,239, 2013 | 245 | 2013 |
| Sacrificial collar method for improved deep trench processing MP Chudzik, I McStay, HH Tews, PS Wrschka US Patent 6,905,944, 2005 | 195 | 2005 |
| Charge transport, optical transparency, microstructure, and processing relationships in transparent conductive indium–zinc oxide films grown by low-pressure metal-organic … A Wang, J Dai, J Cheng, MP Chudzik, TJ Marks, RPH Chang, ... Applied Physics Letters 73 (3), 327-329, 1998 | 159 | 1998 |
| A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process X Chen, S Samavedam, V Narayanan, K Stein, C Hobbs, C Baiocco, W Li, ... 2008 symposium on vlsi technology, 88-89, 2008 | 130 | 2008 |
| A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ... 2011 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2011 | 129 | 2011 |
| Dual metal and dual dielectric integration for metal high-K FETs MP Chudzik, WK Henson, R Jha, Y Liang, R Ramachandran, RS Wise US Patent 8,436,427, 2013 | 123 | 2013 |
| Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for cmos NA Bojarczuk, MP Chudzik, MW Copel, S Guha, R Jammy, V Narayanan, ... US Patent App. 12/166,690, 2008 | 123 | 2008 |
| Sige channel epitaxial development for high-k PFET manufacturability MP Chudzik, DJ Schepis, L Black US Patent 7,622,341, 2009 | 121 | 2009 |
| High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, ... 2007 IEEE symposium on VLSI technology, 194-195, 2007 | 119 | 2007 |
| Band-edge high-performance high-k/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond TC Chen, G Shahidi, S Guha, M Ieong, MP Chudzik, R Jammy, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 178-179, 2006 | 109 | 2006 |
| High performance CMOS circuits, and methods for fabricating the same J Arnold, G Biery, A Callegari, TC Chen, M Chudzik, B Doris, M Gribelyuk, ... US Patent App. 11/323,578, 2007 | 107 | 2007 |
| 22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL S Narasimha, P Chang, C Ortolland, D Fried, E Engbrecht, K Nummy, ... 2012 International Electron Devices Meeting, 3.3. 1-3.3. 4, 2012 | 103 | 2012 |
| Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric AI Chou, MP Chudzik, T Furukawa, O Gluschenkov, PD Kirsch, KC Scheer, ... US Patent 6,930,060, 2005 | 95 | 2005 |
| Scaling the MOSFET gate dielectric: From high-k to higher-k? MM Frank, SB Kim, SL Brown, J Bruley, M Copel, M Hopstaken, ... Microelectronic Engineering 86 (7-9), 1603-1608, 2009 | 90 | 2009 |
| Synthesis and characterization of volatile, fluorine-free β-ketoiminate lanthanide MOCVD precursors and their implementation in low-temperature growth of epitaxial CeO2 buffer … NL Edleman, A Wang, JA Belot, AW Metz, JR Babcock, AM Kawaoka, J Ni, ... Inorganic chemistry 41 (20), 5005-5023, 2002 | 86 | 2002 |
| Method for fabricating nanowires for horizontal gate all around devices for semiconductor applications BS Wood, MG Ward, S Sun, M Chudzik, NS Kim, H Chung, YC Huang, ... US Patent App. 15/395,928, 2017 | 72 | 2017 |
| Deep trench (DT) metal-insulator-metal (MIM) capacitor TW Dyer, EA Cartier, MP Chudzik, N Moumen US Patent 7,741,188, 2010 | 64 | 2010 |
