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Xiaoyu Feng
Xiaoyu Feng
Ph.D. student, Department of Electronic Engineering, Tsinghua University
Verified email at mails.tsinghua.edu.cn
Title
Cited by
Cited by
Year
14.3 a 65nm computing-in-memory-based cnn processor with 2.9-to-35.8 tops/w system energy efficiency using dynamic-sparsity performance-scaling architecture and energy …
J Yue, Z Yuan, X Feng, Y He, Z Zhang, X Si, R Liu, MF Chang, X Li, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 234-236, 2020
822020
Progressive dnn compression: A key to achieve ultra-high weight pruning and quantization rates using admm
S Ye, X Feng, T Zhang, X Ma, S Lin, Z Li, K Xu, W Wen, S Liu, J Tang, ...
arXiv preprint arXiv:1903.09769, 2019
472019
15.2 A 2.75-to-75.9 TOPS/W computing-in-memory NN processor supporting set-associate block-wise zero skipping and ping-pong CIM with simultaneous computation and weight updating
J Yue, X Feng, Y He, Y Huang, Y Wang, Z Yuan, M Zhan, J Liu, JW Su, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 238-240, 2021
442021
STICKER: An energy-efficient multi-sparsity compatible accelerator for convolutional neural networks in 65-nm CMOS
Z Yuan, Y Liu, J Yue, Y Yang, J Wang, X Feng, J Zhao, X Li, H Yang
IEEE Journal of Solid-State Circuits 55 (2), 465-477, 2019
352019
Structadmm: Achieving ultrahigh efficiency in structured pruning for dnns
T Zhang, S Ye, X Feng, X Ma, K Zhang, Z Li, J Tang, S Liu, X Lin, Y Liu, ...
IEEE Transactions on Neural Networks and Learning Systems 33 (5), 2259-2273, 2021
172021
14.2 A 65nm 24.7 µJ/Frame 12.3 mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width …
Z Yuan, Y Yang, J Yue, R Liu, X Feng, Z Lin, X Wu, X Li, H Yang, Y Liu
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 232-234, 2020
122020
PATH: Performance-aware task scheduling for energy-harvesting nonvolatile processors
J Li, Y Liu, H Li, Z Yuan, C Fu, J Yue, X Feng, CJ Xue, J Hu, H Yang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (9 …, 2018
112018
A sparse-adaptive CNN processor with area/performance balanced N-way set-associate PE arrays assisted by a collision-aware scheduler
Z Yuan, J Wang, Y Yang, J Yue, Z Wang, X Feng, Y Wang, X Li, H Yang, ...
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 61-64, 2019
82019
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse
J Yue, Y Liu, Z Yuan, X Feng, Y He, W Sun, Z Zhang, X Si, R Liu, Z Wang, ...
IEEE Journal of Solid-State Circuits, 2022
32022
Admp: An adversarial double masks based pruning framework for unsupervised cross-domain compression
X Feng, Z Yuan, G Wang, Y Liu
arXiv preprint arXiv:2006.04127, 2020
32020
Accelerating CNN-RNN based machine health monitoring on FPGA
X Feng, J Yue, Q Guo, H Yang, Y Liu
2019 IEEE International Conference on Artificial Intelligence Circuits and …, 2019
32019
GAAS: An Efficient Group Associated Architecture and Scheduler Module for Sparse CNN Accelerators
J Wang, Z Yuan, R Liu, X Feng, L Du, H Yang, Y Liu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
12020
An RRAM-Based Digital Computing-in-Memory Macro with Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree
Y He, J Yue, X Feng, Y Huang, H Jia, J Wang, L Zhang, W Sun, H Yang, ...
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022
2022
SEFormer: Structure Embedding Transformer for 3D Object Detection
X Feng, H Du, Y Duan, Y Liu, H Fan
arXiv preprint arXiv:2209.01745, 2022
2022
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications
Y Yang, Y Liu, Z Yuan, W Sun, R Liu, J Wang, J Yue, X Feng, Z Yuan, X Li, ...
IEEE Journal of Solid-State Circuits, 2021
2021
RL Based Network Accelerator Compiler for Joint Compression Hyper-Parameter Search
X Feng, J Yue, Z Yuan, H Yang, Y Liu
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
2020
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