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Jianyi Cheng
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Scalehls: A new scalable high-level synthesis framework on multi-level intermediate representation
H Ye, C Hao, J Cheng, H Jeong, J Huang, S Neuendorffer, D Chen
2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022
682022
Combining dynamic & static scheduling in high-level synthesis
J Cheng, L Josipovic, GA Constantinides, P Ienne, J Wickerson
Proceedings of the 2020 ACM/SIGDA International Symposium on Field …, 2020
532020
Polsca: Polyhedral high-level synthesis with compiler transformations
R Zhao, J Cheng, W Luk, GA Constantinides
2022 32nd International Conference on Field-Programmable Logic and …, 2022
28*2022
DASS: Combining dynamic & static scheduling in high-level synthesis
J Cheng, L Josipović, GA Constantinides, P Ienne, J Wickerson
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021
132021
Finding and finessing static islands in dynamically scheduled circuits
J Cheng, J Wickerson, GA Constantinides
Proceedings of the 2022 ACM/SIGDA International Symposium on Field …, 2022
102022
EASY: Efficient arbiter SYnthesis from multi-threaded code
J Cheng, ST Fleming, YT Chen, JH Anderson, GA Constantinides
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
102019
Efficient memory arbitration in high-level synthesis from multi-threaded code
J Cheng, ST Fleming, YT Chen, J Anderson, J Wickerson, ...
IEEE Transactions on Computers 71 (4), 933-946, 2021
82021
Dynamic inter-block scheduling for HLS
J Cheng, L Josipović, GA Constantinides, J Wickerson
2022 32nd International Conference on Field-Programmable Logic and …, 2022
72022
Dynamic C-slow pipelining for HLS
J Cheng, J Wickerson, GA Constantinides
2022 IEEE 30th Annual International Symposium on Field-Programmable Custom …, 2022
62022
Exploiting the correlation between dependence distance and latency in loop pipelining for hls
J Cheng, J Wickerson, GA Constantinides
2021 31st International Conference on Field-Programmable Logic and …, 2021
62021
Probabilistic scheduling in high-level synthesis
J Cheng, J Wickerson, GA Constantinides
2021 IEEE 29th Annual International Symposium on Field-Programmable Custom …, 2021
62021
Probabilistic optimization for high-level synthesis
J Cheng, J Wickerson, GA Constantinides
The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays …, 2021
32021
Revisiting block-based quantisation: What is important for sub-8-bit LLM inference?
C Zhang, J Cheng, I Shumailov, GA Constantinides, Y Zhao
arXiv preprint arXiv:2310.05079, 2023
22023
Parallelising Control Flow in Dynamic-Scheduling High-Level Synthesis
J Cheng, L Josipović, J Wickerson, GA Constantinides
ACM Transactions on Reconfigurable Technology and Systems, 2023
22023
PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration
A Montgomerie-Corcoran, Z Yu, J Cheng, CS Bouganis
2023 33rd International Conference on Field-Programmable Logic and …, 2023
12023
Fast prototyping next-generation accelerators for new ml models using mase: Ml accelerator system exploration
J Cheng, C Zhang, Z Yu, A Montgomerie-Corcoran, C Xiao, CS Bouganis, ...
arXiv preprint arXiv:2307.15517, 2023
12023
Balancing static islands in dynamically scheduled circuits using continuous petri nets
J Cheng, E Fraca, J Wickerson, GA Constantinides
IEEE Transactions on Computers, 2023
12023
SEER: Super-Optimization Explorer for High-Level Synthesis using E-graph Rewriting
J Cheng, S Coward, L Chelini, R Barbalho, T Drane
Proceedings of the 29th ACM International Conference on Architectural …, 2024
2024
Super-optimization explorer using e-graph rewriting for high-level synthesis
J Cheng, S Coward, L Chelini, R Barbalho, T Drane
US Patent App. 18/396,335, 2024
2024
Program analysis, design space exploration and verification for high-level synthesis via e-graph rewriting
J Cheng, S Coward, L Chelini, R Barbalho, T Drane
US Patent App. 18/396,321, 2024
2024
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