Blocked all-pairs shortest paths algorithm for hybrid CPU-GPU system K Matsumoto, N Nakasato, SG Sedukhin 2011 IEEE International Conference on High Performance Computing and …, 2011 | 52 | 2011 |
Performance tuning of matrix multiplication in OpenCL on different GPUs and CPUs K Matsumoto, N Nakasato, SG Sedukhin 2012 SC Companion: High Performance Computing, Networking Storage and …, 2012 | 40 | 2012 |
Multi-level optimization of matrix multiplication for GPU-equipped systems K Matsumoto, N Nakasato, T Sakai, H Yahagi, SG Sedukhin Procedia Computer Science 4, 342-351, 2011 | 31 | 2011 |
Implementing a Code Generator for Fast Matrix Multiplication in OpenCL on the GPU K Matsumoto, N Nakasato, SG Sedukhin | 25 | 2012 |
A solution of the all-pairs shortest paths problem on the Cell broadband engine processor K Matsumoto, SG Sedukhin IEICE TRANSACTIONS on Information and Systems 92 (6), 1225-1231, 2009 | 17 | 2009 |
Blocked United Algorithm for the All-Pairs Shortest Paths Problem on Hybrid CPU-GPU Systems K MATSUMOTO, N NAKASATO, SG SEDUKHIN IEICE TRANSACTIONS on Information and Systems 95 (12), 2759-2768, 2012 | 16 | 2012 |
Implementation of CG method on GPU cluster with proprietary interconnect TCA for GPU direct communication K Matsumoto, T Hanawa, Y Kodama, H Fujii, T Boku 2015 IEEE International Parallel and Distributed Processing Symposium …, 2015 | 13 | 2015 |
Application of a communication-avoiding generalized minimal residual method to a gyrokinetic five dimensional Eulerian code on many core platforms Y Idomura, T Ina, A Mayumi, S Yamada, K Matsumoto, Y Asahi, ... Proceedings of the 8th Workshop on Latest Advances in Scalable Algorithms …, 2017 | 9 | 2017 |
密結合並列演算加速機構 TCA を用いた GPU 間直接通信による Collective 通信の実装と予備評価 松本和也, 塙敏博, 児玉祐悦, 藤井久史, 朴泰祐 研究報告計算機アーキテクチャ (ARC) 2014 (23), 1-10, 2014 | 7 | 2014 |
Matrix Inversion on the Cell/BE Processor S Yokoyama, K Matsumoto, S Sedukhin 2009 11th IEEE International Conference on High Performance Computing and …, 2009 | 7 | 2009 |
Implementation and performance evaluation of a communication-avoiding gmres method for stencil-based code on gpu cluster K Matsumoto, Y Idomura, T Ina, A Mayumi, S Yamada The Journal of Supercomputing 75, 8115-8146, 2019 | 5 | 2019 |
Evaluation of FFT for GPU Cluster Using Tightly Coupled Accelerators Architecture T Hanawa, H Fujii, N Fujita, T Odajima, K Matsumoto, T Boku 2015 IEEE International Conference on Cluster Computing, 635-641, 2015 | 5 | 2015 |
Implementing Level-3 BLAS Routines in OpenCL on Different Processing Units K Matsumoto, N Nakasato, S Sedukhin Technical Report, The University of Aizu, 2014 | 5 | 2014 |
密結合並列演算加速機構 TCA による GPU 間直接通信における Collective 通信の実装と性能評価 松本和也, 塙敏博, 児玉祐悦, 藤井久史, 朴泰祐 情報処理学会論文誌コンピューティングシステム (ACS) 8 (4), 36-49, 2015 | 3 | 2015 |
The Algebraic Path Problem on the Cell/BE Processor K Matsumoto, SG Sedukhin The University of Aizu, Tech. Rep 2, 2010, 2010 | 3 | 2010 |
Matrix multiply-add in min-plus algebra on a short-vector SIMD processor of Cell/BE K Matsumoto, SG Sedukhin 2010 First International Conference on Networking and Computing, 272-274, 2010 | 3 | 2010 |
Effectiveness of performance tuning techniques for general matrix multiplication on the pezy-sc2 K Matsumoto, N Nakasato, T Hishinuma Proceedings of the 10th International Symposium on Highly-Efficient …, 2019 | 2 | 2019 |
Improving Strong-Scaling on GPU Cluster Based on Tightly Coupled Accelerators Architecture T Hanawa, H Fujii, N Fujita, T Odajima, K Matsumoto, Y Kodama, T Boku 2015 IEEE International Conference on Cluster Computing, 88-91, 2015 | 2 | 2015 |
Brain-inspired co-design of algorithm/architecture for CNN accelerators S Sedukhin, K Matsumoto, Y Tomioka 2019 8th International Congress on Advanced Applied Informatics (IIAI-AAI …, 2019 | 1 | 2019 |
密結合並列演算加速機構 TCA を用いた GPU 間直接通信による Collective 通信の実装と性能評価 松本和也, 塙敏博, 児玉祐悦, 藤井久史, 朴泰祐 ハイパフォーマンスコンピューティングと計算科学シンポジウム論文集 2015, 120-128, 2015 | 1 | 2015 |