| Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU S Kumar, S Chellappa, LT Clark 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 814-817, 2015 | 23 | 2015 |
| Methodology to optimize critical node separation in hardened flip-flops S Shambhulingaiah, S Chellappa, S Kumar, LT Clark Fifteenth International Symposium on Quality Electronic Design, 486-493, 2014 | 13 | 2014 |
| A 12nm 137 TOPS/W Digital Compute-In-Memory using Foundry 8T SRAM Bitcell supporting 16 Kernel Weight Sets for AI Edge Applications G Jedhe, C Deshpande, S Kumar, CX Xue, Z Guo, R Garg, KS Jway, ... 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 11 | 2023 |
| A 12-nm 0.62-1.61 mW Ultra-Low Power Digital CIM-based Deep-Learning System for End-to-End Always-on Vision EJ Chang, CX Xue, C Deshpande, G Jedhe, J Liang, CC Cheng, HW Lin, ... 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 5 | 2023 |
| 20.1 NVE: A 3nm 23.2 TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices ME Shih, SW Hsieh, PY Tsai, MH Lin, PK Tsung, EJ Chang, J Liang, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 360-362, 2024 | 4 | 2024 |
| Sequential state elements radiation hardened by design LT Clark, S Shambhulingaiah, S Kumar, C Ramamurthy US Patent 9,054,688, 2015 | 4 | 2015 |
| A 5nm Fin-FET 2G-search/s 512-entry x 220-bit TCAM with Single Cycle Entry Update Capability for Data Center ASICs C Deshpande, R Garg, G Jedhe, G Narvekar, S Kumar 2021 Symposium on VLSI Circuits, 1-2, 2021 | 2 | 2021 |
| Dynamic capacitance balancing VP Schuppe, S Kumar, DM Malaviya, HH Parate US Patent 9,570,157, 2017 | 1 | 2017 |
| DYNAMICALLY GATED SEARCH LINES FOR LOW-POWER MULTI-STAGE CONTENT ADDRESSABLE MEMORY SK Chetan Deshpande US Patent 11,967,377 B2, 2023 | | 2023 |
| Radiation hardened pulse based d flip flop design S Kumar Arizona State University, 2014 | | 2014 |
