Manil Dev Gomony
Manil Dev Gomony
Researcher, Bell Labs
Verified email at nokia-bell-labs.com - Homepage
Title
Cited by
Cited by
Year
Virtual Execution Platforms for Mixed-Time-Criticality Applications: The CompSOC Architecture and Design Flow
K Goossens, A Azevedo, K Chandrasekar, MD Gomony, S Goossens, ...
99*2012
Architecture and Optimal Configuration of a Real-Time Multi-Channel Memory Controller
MD Gomony, B Akesson, K Goossens
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
462013
Leveraging 802.11 n frame aggregation to enhance QoS and power consumption in Wi-Fi networks
D Camps-Mur, MD Gomony, X PÚRez-Costa, S Sallent-Ribes
Computer Networks 56 (12), 2896-2911, 2012
272012
A globally arbitrated memory tree for mixed-time-criticality systems
MD Gomony, J Garside, B Akesson, N Audsley, K Goossens
IEEE Transactions on Computers 66 (2), 212-225, 2016
232016
A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems
MD Gomony, J Garside, B Akesson, N Audsley, K Goossens
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 193-198, 2015
212015
DRAM Selection and Configuration for Real-Time Mobile Systems
MD Gomony, C Weis, B Akesson, N Wehn, K Goossens
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
192012
A real-time multichannel memory controller and optimal mapping of memory clients to memory channels
MD Gomony, B Akesson, K Goossens
ACM Transactions on Embedded Computing Systems (TECS) 14 (2), 1-27, 2015
162015
Coupling tdm noc and dram controller for cost and performance optimization of real-time systems
MD Gomony, B Akesson, K Goossens
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
102014
Method for operating a wireless network and a wireless network
DC Mur, M Gomony, XP Costa
US Patent 8,873,393, 2014
32014
An adaptive solution for power efficiency and QoS optimization in WLAN 802.11 n
MD Gomony
32010
μ-Genie: A Framework for Memory-Aware Spatial Processor Architecture Co-Design Exploration
G Stramondo, MD Gomony, B Kozicki, C De Laat, AL Varbanescu
2020 23rd Euromicro Conference on Digital System Design (DSD), 180-184, 2020
2020
A 28-nm Coarse Grain 2D-Reconfigurable Array With Data Forwarding
S Smets, MD Gomony, M Jivanescu, T GoedemÚ, M Verhelst
IEEE Solid-State Circuits Letters 3, 226-229, 2020
2020
A Reconfigurable Architecture for Posit Arithmetic
S Sarkar, PM Velayuthan, MD Gomony
2019 22nd Euromicro Conference on Digital System Design (DSD), 82-87, 2019
2019
Quater-imaginary base for complex number arithmetic circuits
S Sarkar, MD Gomony
2018 Design, Automation & Test in Europe Conference & Exhibition (DATEá…, 2018
2018
A reconfigurable mixed-time-criticality SDRAM controller
SLM Goossens
Technische Universiteit Eindhoven, 2015
2015
Scalable and bandwidth-efficient memory subsystem design for real-time systems
MD Gomony
Technische Universiteit Eindhoven, 2015
2015
An optimal multi-channel memory controller for real-time systems
MD Gomony, KB Akesson, KGW Goossens
ICT. OPEN 2013, November 27-28, 2013, Eindhoven, The Netherlands, 2013
2013
A parallel-access method for 3D-stacked DRAMs
MD Gomony, B ┼kesson, K Goossens
Memory 1, 1.2, 2011
2011
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Articles 1–18