Chun Wing Yeung
Chun Wing Yeung
IBM Research, UC Berkeley
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Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ...
2017 symposium on VLSI technology, T230-T231, 2017
Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation
AI Khan, CW Yeung, C Hu, S Salahuddin
2011 International Electron Devices Meeting, 11.3. 1-11.3. 4, 2011
Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages
A Padilla, CW Yeung, C Shin, C Hu, TJK Liu
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Single crystal functional oxides on silicon
SR Bakaul, CR Serrao, M Lee, CW Yeung, A Sarker, SL Hsu, AK Yadav, ...
Nature communications 7 (1), 10547, 2016
Ultrathin body InAs tunneling field-effect transistors on Si substrates
AC Ford, CW Yeung, S Chuang, HS Kim, E Plis, S Krishna, C Hu, A Javey
Applied Physics Letters 98 (11), 2011
Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond
CC Liu, E Franke, Y Mignot, R Xie, CW Yeung, J Zhang, C Chi, C Zhang, ...
Nature Electronics 1 (10), 562-569, 2018
Channel geometry impact and narrow sheet effect of stacked nanosheet
CW Yeung, J Zhang, R Chao, O Kwon, R Vega, G Tsutsui, X Miao, ...
2018 IEEE international electron devices meeting (IEDM), 28.6. 1-28.6. 4, 2018
Low power negative capacitance FETs for future quantum-well body technology
CW Yeung, AI Khan, A Sarker, S Salahuddin, C Hu
2013 International symposium on VLSI technology, systems and application …, 2013
Dense electron system from gate-controlled surface metal–insulator transition
K Liu, D Fu, J Cao, J Suh, KX Wang, C Cheng, DF Ogletree, H Guo, ...
Nano letters 12 (12), 6272-6277, 2012
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor
J Zhang, T Ando, CW Yeung, M Wang, O Kwon, R Galatage, R Chao, ...
2017 IEEE International Electron Devices Meeting (IEDM), 22.1. 1-22.1. 4, 2017
Programming characteristics of the steep turn-on/off feedback FET (FBFET)
CW Yeung, A Padilla, TJK Liu, C Hu
2009 Symposium on VLSI Technology, 176-177, 2009
Air spacer for 10nm FinFET CMOS and beyond
K Cheng, C Park, C Yeung, S Nguyen, J Zhang, X Miao, M Wang, ...
2016 IEEE International Electron Devices Meeting (IEDM), 17.1. 1-17.1. 4, 2016
Device design considerations for ultra-thin body non-hysteretic negative capacitance FETs
CW Yeung, AI Khan, S Salahuddin, C Hu
2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S), 1-2, 2013
Semiconductor device and method of forming the semiconductor device
RH Chao, H Jagannathan, CH Lee, CW Yeung, J Zhang
US Patent 10,079,233, 2018
Non-hysteretic Negative Capacitance FET with Sub-30mV/dec Swing over 106X Current Range and ION of 0.3 mA/μm without Strain Enhancement at 0.3 V VDD
CW Yeung, AI Khan, JY Cheng, S Salahuddin, C Hu
Conf. Simul. Semicond. Processes Devices, 257, 2012
Quantum well InAs/AlSb/GaSb vertical tunnel FET with HSQ mechanical support
Y Zeng, CI Kuo, C Hsu, M Najmzadeh, A Sachid, R Kapadia, C Yeung, ...
IEEE Transactions on Nanotechnology 14 (3), 580-584, 2015
Sacrificial cap for forming semiconductor contact
P Adusumilli, Z Liu, S Mochizuki, J Yang, CW Yeung
US Patent 9,805,989, 2017
Nanosheet FET with wrap-around inner spacer
CW Yeung, C Zhang
US Patent 9,842,914, 2017
Uniform low-k inner spacer module in gate-all-around (GAA) transistors
RH Chao, CH Lee, CW Yeung, J Zhang
US Patent 10,243,060, 2019
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