| Scalability of network-on-chip communication architecture for 3-D meshes AY Weldezion, M Grange, D Pamunuwa, Z Lu, A Jantsch, R Weerasekera, ... 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 114-123, 2009 | 78 | 2009 |
| Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach AM Rahmani, MH Haghbayan, A Kanduri, AY Weldezion, P Liljeberg, ... 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 65 | 2015 |
| Dark silicon aware power management for manycore systems under dynamic workloads MH Haghbayan, AM Rahmani, AY Weldezion, P Liljeberg, J Plosila, ... 2014 IEEE 32nd International Conference on Computer Design (ICCD), 509-512, 2014 | 54 | 2014 |
| 3-D memory organization and performance analysis for multi-processor network-on-chip architecture AY Weldezion, Z Lu, R Weerasekera, H Tenhunen 2009 IEEE International Conference on 3D System Integration, 1-7, 2009 | 30 | 2009 |
| Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits AY Weldezion, R Weerasekera, D Pamunuwa, L Zheng, H Tenhunen DATE'09 Friday Workshops-3D Integration-Technology, Architecture, Design …, 2009 | 18 | 2009 |
| A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns AY Weldezion, M Grange, D Pamunuwa, A Jantsch, H Tenhunen 2013 IEEE International 3D Systems Integration Conference (3DIC), 1-5, 2013 | 10 | 2013 |
| NoD: Network-on-Die as a standalone NoC for heterogeneous many-core systems in 2.5 D ICs M Ebrahimi, AY Weldezion, M Daneshtalab 2017 19th International Symposium on Computer Architecture and Digital …, 2017 | 9 | 2017 |
| Power integrity optimization of 3D chips stacked through TSVs W Ahmad, LR Zheng, R Weerasekera, Q Chen, AY Weldezion, ... 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging …, 2009 | 9 | 2009 |
| Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh M Grange, AY Weldezion, D Pamunuwa, R Weerasekera, Z Lu, A Jantsch, ... 2009 IEEE International Conference on 3D System Integration, 1-7, 2009 | 8 | 2009 |
| Zero-load predictive model for performance analysis in deflection routing NoCs AY Weldezion, M Grange, A Jantsch, H Tenhunen, D Pamunuwa Microprocessors and Microsystems 39 (8), 634-647, 2015 | 7 | 2015 |
| Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks M Grange, R Weerasekera, D Pamunuwa, A Jantsch, AY Weldezion Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on …, 2011 | 7 | 2011 |
| Automated power and latency management in heterogeneous 3d nocs AY WeldeZion, M Ebrahimi, M Daneshtalab, H Tenhunen Proceedings of the 8th International Workshop on Network on Chip …, 2015 | 6 | 2015 |
| Design space exploration of clock-pumping techniques to reduce through-silicon-via (TSV) manufacturing cost in 3-d integration AY Weldezion, R Weerasekara, H Tenhunen 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC), 19-22, 2012 | 2 | 2012 |
| Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture AY Weldezion KTH Royal Institute of Technology, 2016 | 1 | 2016 |
| Adaptive Power Capping for Dark Silicon Many-core Systems MH Haghbayan, AM Rahmani, AY Weldezion, P Liljeberg, J Plosila, ... | | 2016 |
| A Business Model for a University Based High-tech Research Center: Innovation-Centric Research Model AY Weldezion MBA Thesis, UTU- University of Turku School of Economics - Turun yliopisto, 2012 | | 2012 |
| Vital Signs Acquisition and Communication System Board Implementation AY Weldezion Masters thesis, School for Information and Communication Technology, KTH …, 2007 | | 2007 |
| Communication System Design IK2209 Autumn 2007 New Shopping Dimension Designing documentation E Remander, H Toufaili, AY Weldezion, AFMS Kabir, YL Wu, E Romanidis, ... | | 2007 |
Axel JantschTU Wien, Vienna, Austria (Vienna University of Technology)Verified email at tuwien.ac.at
