Prof. Dr. Murat Aşkar
Prof. Dr. Murat Aşkar
Izmir University of Economics, Department of Electrical & Electronics Engineering
Verified email at
Cited by
Cited by
Real-Time Motor Fault Detection by 1-D Convolutional Neural Networks
T Ince, S Kiranyaz, L Eren, M Askar, M Gabbouj
IEEE Transactions on Industrial Electronics 63 (11), 7067 - 7075, 2016
A Recursive Algorithm for the Bayes Solution of the Smoothing Problem
M Askar, H Derin
IEEE Transactions on Automatic Control 26 (2), 558-561, 1981
A high speed ASIC implementation of the Rijndael algorithm
R Sever, AN Ismailoglu, YC Tekmen, M Askar
2004 IEEE International Symposium on Circuits and Systems, 541-544, 2004
Adaptive voice-feature-enhanced matchmaking method and system
A Manas, V Ozturk, U Emekli, GB Akar, B Kepenekci, M Askar, T Ciloglu
US Patent App. 11/981,010, 2008
A high speed FPGA implementation of the Rijndael algorithm
R Sever, AN Ismailglu, YC Tekmen, M Askar, B Okcan
EUROMICRO Symposium on Digital System Design, 2004. (DSD 2004), 358 - 362, 2004
Two fast RSA implementations using high-radix montgomery algorithm
S Yesil, AN Ismailoglu, YC Tekmen, M Askar
2004 IEEE International Symposium on Circuits and Systems 2, 557-560, 2004
Practical performance of planar spiral inductors
A Telli, IE Demir, M Askar
Proceedings of the 2004 11th IEEE International Conference on Electronics†…, 2004
CMOS LNA design for LEO space S-band applications
A Telli, M Askar
CCECE 2003-Canadian Conference on Electrical and Computer Engineering†…, 2003
Design and SystemC Implementation of a Crypto Processor for AES and DES Algorithms
M Askar, T Egemen
Information Security and Cryptology Conference with International Participation, 2007
Design and FPGA implementation of Hash processor
M Aşkar, TŞ «elebi
Proceedings of the Information Security & Cryptology Conference with†…, 2007
Incremental design of high complexity FIR filters by genetic algorithms
M Oner, M Askar
ISSPA'99. Proceedings of the Fifth International Symposium on Signal†…, 1999
A wired-AND current-mode logic circuit technique in CMOS for low-voltage, high-speed and mixed-signal VLSIC
IE Ungan, M Askar
Analog Integrated Circuits and Signal Processing 14 (1-2), 59-70, 1997
Motor current signature analysis via four-channel FIR filter banks
L Eren, M Aşkar, MJ Devaney
Measurement 89, 322-327, 2016
CMOS LNA design for system-on-chip receiver stages
A Telli, M Askar
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated†…, 2004
Turkish small satellite program: Goals and policies
M Aşkar, O Tekinalp
Acta Astronautica 46 (2-6), 375-378, 2000
8◊ 8-bit multiplier designed with a new wave-pipelining scheme
R Sever, M Askar
Proceedings of 2010 IEEE International Symposium on Circuits and Systems†…, 2010
Trellis coded quantization for data hiding
E Esen, AA Alatan, M Askar
The IEEE Region 8 EUROCON 2003. Computer as a Tool. 2, 384-388, 2003
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
AN Ismailoglu, M Askar
7th WSEAS Int. Conf. on Electronics, Hardware, Wireless and Optical†…, 2008
Application of bit-level pipelining to delay insensitive null convention adders
AN Ismailoglu, M Askar
2007 IEEE International Symposium on Circuits and Systems, 3259-3262, 2007
CMOS planar spiral inductor modeling and low noise amplifier design
A Telli, S Demir, M Askar
Microelectronics journal 37 (1), 71-78, 2006
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