| ADEPOS: anomaly detection based power saving for predictive maintenance using edge computing SK Bose, B Kar, M Roy, PK Gopalakrishnan, A Basu Proceedings of the 24th asia and south pacific design automation conference …, 2019 | 49 | 2019 |
| A stacked autoencoder neural network based automated feature extraction method for anomaly detection in on-line condition monitoring M Roy, SK Bose, B Kar, PK Gopalakrishnan, A Basu 2018 IEEE Symposium Series on Computational Intelligence (SSCI), 1501-1507, 2018 | 38 | 2018 |
| ADEPOS: A novel approximate computing framework for anomaly detection systems and its implementation in 65-nm CMOS SK Bose, B Kar, M Roy, PK Gopalakrishnan, L Zhang, A Patil, A Basu IEEE Transactions on Circuits and Systems I: Regular Papers 67 (3), 913-926, 2019 | 20 | 2019 |
| STAIRoute: Global routing using monotone staircase channels B Kar, S Sur-Kola, C Mandal 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 90-95, 2013 | 8 | 2013 |
| A faster hierarchical balanced bipartitioner for VLSI floorplans using monotone staircase cuts B Kar, S Sur-Kolay, SH Rangarajan, CR Mandal Progress in VLSI Design and Test: 16th International Symposium, VDAT 2012 …, 2012 | 8 | 2012 |
| ADIC: Anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computing B Kar, PK Gopalakrishnan, SK Bose, M Roy, A Basu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (12 …, 2020 | 7 | 2020 |
| Global Routing using Monotone Staircases with Minimal Bends B Kar, S Sur-Kolay, C Mandal 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 4 | 2014 |
| Live demonstration: Autoencoder-based predictive maintenance for IoT PK Gopalakrishnan, B Kar, SK Bose, M Roy, A Basu 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2019 | 3 | 2019 |
| A New Method for Defining Monotone Staircases in VLSI Floorplans B Kar, S Sur-Kolay, C Mandal 2015 IEEE Computer Society Annual Symposium on VLSI, 107-112, 2015 | 2 | 2015 |
| A novel architecture for QPSK modulation based on time-mode signal processing S Saha, B Kar, S Sur-Kolay 18th International Symposium on VLSI Design and Test, 1-6, 2014 | 2 | 2014 |
| Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning B Kar, S Sur-Kolay, C Mandal arXiv preprint arXiv:1811.05161, 2018 | | 2018 |
| Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model B Kar, S Sur-Kolay, C Mandal arXiv preprint arXiv:1810.12789, 2018 | | 2018 |
| STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction B Kar, S Sur-Kolay, C Mandal arXiv preprint arXiv:1810.10412, 2018 | | 2018 |
| Design for Manufacturability aware Early Global Routing B Kar IIT, Kharagpur, 2017 | | 2017 |
| An early global routing framework for uniform wire distribution in SoCs B Kar, S Sur-Kolay, C Mandal 2016 29th IEEE International System-on-Chip Conference (SOCC), 139-144, 2016 | | 2016 |
| A Novel EPE Aware Hybrid Global Route Planner after Floorplanning B Kar, S Sur-Kolay, C Mandal 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | | 2016 |
| Technical Program Committee Members A Shrivastava, A Acharya, S Surat, A Mondal, NITA Pradesh, A Singh, ... | | |
Chittaranjan MandalDept of Computer Sc & Engg, IIT KharagpurVerified email at iitkgp.ac.in
