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CK Cheng
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An O-tree representation of non-slicing floorplan and its applications
PN Guo, CK Cheng, T Yoshimura
Proceedings 1999 design automation conference (Cat. No. 99CH36361), 268-273, 1999
5411999
Corner block list: An effective and efficient topological representation of non-slicing floorplan
X Hong, G Huang, Y Cai, J Gu, S Dong, CK Cheng, J Gu
IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000
4572000
Optimal wire sizing and buffer insertion for low power and a generalized delay model
J Lillis, CK Cheng, TTY Lin
IEEE Journal of Solid-State Circuits 31 (3), 437-447, 1996
4101996
Ratio cut partitioning for hierarchical designs
YC Wei, CK Cheng
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1991
3311991
Towards efficient hierarchical designs by ratio cut partitioning
YC Wei, CK Cheng
1989 IEEE International Conference on Computer-Aided Design. Digest of …, 1989
2961989
Module placement based on resistive network optimization
CK Cheng, ES Kuh
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1984
2331984
An improved two-way partitioning algorithm with stable performance (VLSI)
CK Cheng, YCA Wei
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1991
2231991
New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
J Lillis, CK Cheng, TTY Lin, CY Ho
Proceedings of the 33rd annual Design Automation Conference, 395-400, 1996
1681996
Floorplanning using a tree representation
PN Guo, T Takahashi, CK Cheng, T Yoshimura
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001
1352001
Performance-driven Steiner tree algorithms for global routing
X Hong, T Xue, ES Kuh, CK Cheng, J Huang
30th ACM/IEEE Design Automation Conference, 177-181, 1993
1281993
A general purpose multiple way partitioning algorithm
CW Yeh, CK Cheng, TTY Lin
Proceedings of the 28th ACM/IEEE Design Automation Conference, 421-426, 1991
1211991
Area minimization of power distribution network using efficient nonlinear programming techniques
X Wu, X Hon, Y Ca, CK Cheng, J Gu, W Dai
IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE …, 2001
1182001
Interconnect delay driven placement and routing of an integrated circuit design
CK Cheng, SZ Yao
US Patent 6,327,693, 2001
1062001
Floorplan representations: Complexity and connections
B Yao, H Chen, CK Cheng, R Graham
ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (1 …, 2003
1022003
An enhanced perturbing algorithm for floorplan design using the O-tree representation
Y Pang, CK Cheng, T Yoshimura
Proceedings of the 2000 international symposium on physical design, 168-173, 2000
1002000
Block placement with symmetry constraints based on the O-tree non-slicing representation
Y Pang, F Balasa, K Lampaert, CK Cheng
Proceedings of the 37th Annual Design Automation Conference, 464-467, 2000
982000
Replace: Advancing solution quality and routability validation in global placement
CK Cheng, AB Kahng, I Kang, L Wang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
922018
Simultaneous routing and buffer insertion for high performance interconnect
J Lillis, CK Cheng, TTY Lin
Proceedings of the Sixth Great Lakes Symposium on VLSI, 148-153, 1996
871996
A global router using an efficient approximate multicommodity multiterminal flow algorithm
RC Carden IV, CK Cheng
Proceedings of the 28th ACM/IEEE Design Automation Conference, 316-321, 1991
861991
An efficient timing-driven global routing algorithm
J Huang, XL Hong, CK Cheng, ES Kuh
Proceedings of the 30th international Design Automation Conference, 596-600, 1993
851993
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