David Blaauw
David Blaauw
Professor of Electrical Engineering and Computer Science, University of Michigan
Verified email at
Cited by
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Razor: A low-power pipeline based on circuit-level timing speculation
D Ernst, NS Kim, S Das, S Pant, R Rao, T Pham, C Ziesler, D Blaauw, ...
Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003
Leakage current: Moore's law meets static power
NS Kim, T Austin, D Baauw, T Mudge, K Flautner, JS Hu, MJ Irwin, ...
computer 36 (12), 68-75, 2003
Drowsy caches: simple techniques for reducing leakage power
K Flautner, NS Kim, S Martin, D Blaauw, T Mudge
ACM SIGARCH Computer architecture news 30 (2), 148-157, 2002
Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits
RG Dreslinski, M Wieckowski, D Blaauw, D Sylvester, T Mudge
Proceedings of the IEEE 98 (2), 253-266, 2010
RazorII: In situ error detection and correction for PVT and SER tolerance
S Das, C Tokunaga, S Pant, WH Ma, S Kalaiselvan, K Lai, DM Bull, ...
IEEE Journal of Solid-State Circuits 44 (1), 32-48, 2008
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
SM Martin, K Flautner, T Mudge, D Blaauw
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002
Statistical timing analysis for intra-die process variations with spatial correlations
A Agarwal, D Blaauw, V Zolotov
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
A self-tuning DVS processor using delay-error detection and correction
S Das, D Roberts, S Lee, S Pant, D Blaauw, T Austin, K Flautner, T Mudge
IEEE Journal of Solid-State Circuits 41 (4), 792-804, 2006
Theoretical and practical limits of dynamic voltage scaling
B Zhai, D Blaauw, D Sylvester, K Flautner
Proceedings of the 41st annual Design Automation Conference, 868-873, 2004
Razor: circuit-level correction of timing errors for low-power operation
D Ernst, S Das, S Lee, D Blaauw, T Austin, T Mudge, NS Kim, K Flautner
IEEE Micro 24 (6), 10-20, 2004
Statistical timing analysis: From basic principles to state of the art
D Blaauw, K Chopra, A Srivastava, L Scheffer
IEEE transactions on computer-aided design of integrated circuits and …, 2008
Hierarchical analysis of power distribution networks
M Zhao, RV Panda, SS Sapatnekar, T Edwards, R Chaudhry, D Blaauw
Proceedings of the 37th Annual Design Automation Conference, 150-155, 2000
A portable 2-transistor picowatt temperature-compensated voltage reference operating at 0.5 V
M Seok, G Kim, D Blaauw, D Sylvester
IEEE Journal of Solid-State Circuits 47 (10), 2534-2545, 2012
Neural cache: Bit-serial in-cache acceleration of deep neural networks
C Eckert, X Wang, J Wang, A Subramaniyan, R Iyer, D Sylvester, ...
2018 ACM/IEEE 45Th annual international symposium on computer architecture …, 2018
Statistical analysis and optimization for VLSI: Timing and power
A Srivastava, D Sylvester, D Blaauw
Springer, 2005
Compute caches
S Aga, S Jeloka, A Subramaniyan, S Narayanasamy, D Blaauw, R Das
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
Analysis and mitigation of variability in subthreshold design
B Zhai, S Hanson, D Blaauw, D Sylvester
Proceedings of the 2005 international symposium on Low power electronics and …, 2005
A highly resilient routing algorithm for fault-tolerant NoCs
D Fick, A DeOrio, G Chen, V Bertacco, D Sylvester, D Blaauw
2009 Design, Automation & Test in Europe Conference & Exhibition, 21-26, 2009
A 28 nm configurable memory (TCAM/BCAM/SRAM) using push-rule 6T bit cell enabling logic-in-memory
S Jeloka, NB Akesh, D Sylvester, D Blaauw
IEEE Journal of Solid-State Circuits 51 (4), 1009-1021, 2016
Ultralow-voltage, minimum-energy CMOS
S Hanson, B Zhai, K Bernstein, D Blaauw, A Bryant, L Chang, KK Das, ...
IBM journal of research and development 50 (4.5), 469-490, 2006
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