| Semiconductor device and method for manufacturing the same K Motoyama US Patent 6,900,539, 2005 | 56 | 2005 |
| BEOL process integration for the 7 nm technology node T Standaert, G Beique, HC Chen, ST Chen, B Hamieh, J Lee, ... 2016 IEEE international interconnect technology conference/advanced …, 2016 | 37 | 2016 |
| Suppression of bimodal stress-induced voiding using high-diffusive dopant from Cu-alloy seed layer T Tonegawa, M Hiroi, K Motoyama, K Fujii, H Miyamoto Proceedings of the IEEE 2003 International Interconnect Technology …, 2003 | 30 | 2003 |
| Copper interconnect with CVD liner and metallic cap FH Baumann, CK Hu, AH Simon, T Bolom, K Motoyama, CC Niu US Patent 9,059,176, 2015 | 28 | 2015 |
| Tradeoff characteristics between resistivity and reliability for scaled-down Cu-based interconnects S Yokogawa, K Kikuta, H Tsuchiya, T Takewaki, M Suzuki, H Toyoshima, ... IEEE transactions on electron devices 55 (1), 350-357, 2007 | 27 | 2007 |
| A high reliability copper dual-damascene interconnection with direct-contact via structure K Ueno, M Suzuki, A Matsumoto, K Motoyama, N Oda, H Miyamoto, ... AIP Conference Proceedings 612 (1), 49-60, 2002 | 25 | 2002 |
| Semiconductor device and method for manufacturing the same K Motoyama US Patent 7,566,975, 2009 | 15 | 2009 |
| PVD Cu reflow seed process optimization for defect reduction in nanoscale Cu/low-k dual damascene interconnects K Motoyama, O Van Der Straten, J Maniscalco, M He Journal of The Electrochemical Society 160 (12), D3211, 2013 | 14 | 2013 |
| Discrete Study of ALD TaN on Via and Line for Low Resistive and High Reliable Cu/Low-k Interconnects and Other Applications K Motoyama, K Fujii ECS Journal of Solid State Science and Technology 1 (6), P303, 2012 | 12 | 2012 |
| ALD and PVD tantalum nitride barrier resistivity and their significance in via resistance trends O Van Der Straten, X Zhang, K Motoyama, C Penny, J Maniscalco, ... ECS Transactions 64 (9), 117, 2014 | 11 | 2014 |
| Semiconductor device including an insulating layer, and method of forming the semiconductor device K Motoyama, O van der Straten US Patent App. 14/066,360, 2014 | 11 | 2014 |
| A novel resistivity measurement technique for scaled-down Cu interconnects implemented to reliability-focused automobile applications S Yokogawa, K Kikuta, H Tsuchiya, T Takewaki, M Suzuki, H Toyoshima, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 9 | 2006 |
| Performance of ultrathin alternative diffusion barrier metals for next-Generation BEOL technologies, and their effects on reliability T Nogami, M Chae, C Penny, T Shaw, H Shobha, J Li, S Cohen, CK Hu, ... IEEE International Interconnect Technology Conference, 223-226, 2014 | 6 | 2014 |
| A robust 45 nm-node, dual damascene interconnects with high quality cu/barrier interface by a novel oxygen absorption process M Abe, M Tada, H Ohtake, N Furutake, M Narihiro, K Arai, T Takeuchi, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 77-80, 2005 | 6 | 2005 |
| Full-0.56/spl mu/m pitch copper interconnects for a high performance 0.15-/spl mu/m CMOS logic device M Iguchi, T Takewaki, Y Matsubara, Y Kunimune, N Ito, Y Tsuchiya, ... International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999 | 6 | 1999 |
| Copper interconnect with CVD liner and metallic cap FH Baumann, T Bolom, CK Hu, K Motoyama, C Niu, AH Simon US Patent 9,111,938, 2015 | 5 | 2015 |
| Hybridization of XRF/XPS and scatterometry for Cu CMP process control B L'Herron, R Chao, K Kim, WT Lee, K Motoyama, B Deprospo, ... Metrology, Inspection, and Process Control for Microlithography XXIX 9424 …, 2015 | 5 | 2015 |
| A metallurgical prescription for electromigration (EM) reliability improvment in scaled-down, Cu dual damascene interconnects M Tada, M Abe, H Ohtake, N Furutake, T Tonegawa, K Motoyama, ... 2006 International Interconnect Technology Conference, 89-91, 2006 | 5 | 2006 |
| Feasibility study of a novel molecular-pore-stacking (MPS), SiOCH film in fully-scale-down, 45nm-node Cu damascene interconnects M Tada, H Ohtake, M Narihiro, F Ito, T Taiji, M Tohara, K Motoyama, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 18-19, 2005 | 5 | 2005 |
| Structure and fabrication method for electromigration immortal nanoscale interconnects BD Briggs, LA Clevenger, K Motoyama, M Rizzolo US Patent 9,418,934, 2016 | 3 | 2016 |
