| A floating-gate-based field-programmable analog array A Basu, S Brink, C Schlottmann, S Ramakrishnan, C Petre, S Koziol, ... IEEE Journal of Solid-State Circuits 45 (9), 1781-1794, 2010 | 144 | 2010 |
| A Learning-Enabled Neuron Array IC Based Upon Transistor Channel Models of Biological Phenomena S Brink, S Nease, P Hasler, S Ramakrishnan, R Wunderlich, A Basu, ... IEEE, 0 | 103 | |
| Synergistic Gating of Electro‐Iono‐Photoactive 2D Chalcogenide Neuristors: Coexistence of Hebbian and Homeostatic Synaptic Metaplasticity RA John, F Liu, NA Chien, MR Kulkarni, C Zhu, Q Fu, A Basu, Z Liu, ... Advanced Materials 30 (25), 1800220, 2018 | 97 | 2018 |
| Neural dynamics in reconfigurable silicon A Basu, S Ramakrishnan, C Petre, S Koziol, S Brink, PE Hasler IEEE Transactions on Biomedical Circuits and Systems 4 (5), 311-319, 2010 | 73 | 2010 |
| A charge-based low-power high-SNR capacitive sensing interface circuit SY Peng, MS Qureshi, PE Hasler, A Basu, FL Degertekin IEEE Transactions on Circuits and Systems I: Regular Papers 55 (7), 1863-1872, 2008 | 70 | 2008 |
| A charge-based low-power high-SNR capacitive sensing interface circuit SY Peng, MS Qureshi, PE Hasler, A Basu, FL Degertekin IEEE Transactions on Circuits and Systems I: Regular Papers 55 (7), 1863-1872, 2008 | 70 | 2008 |
| Silicon spiking neurons for hardware implementation of extreme learning machines A Basu, S Shuo, H Zhou, MH Lim, GB Huang Neurocomputing 102, 125-134, 2013 | 69 | 2013 |
| A 128-channel extreme learning machine-based neural decoder for brain machine interfaces Y Chen, E Yao, A Basu IEEE transactions on biomedical circuits and systems 10 (3), 679-692, 2015 | 64 | 2015 |
| Nullcline-based design of a silicon neuron A Basu, PE Hasler IEEE Transactions on Circuits and Systems I: Regular Papers 57 (11), 2938-2947, 2010 | 58 | 2010 |
| RASP 2.8: A new generation of floating-gate based field programmable analog array A Basu, CM Twigg, S Brink, P Hasler, C Petre, S Ramakrishnan, S Koziol, ... 2008 IEEE Custom Integrated Circuits Conference, 213-216, 2008 | 47 | 2008 |
| Hardware and software infrastructure for a family of floating-gate based FPAAs S Koziol, C Schlottmann, A Basu, S Brink, C Petre, B Degnan, ... Proceedings of 2010 IEEE international symposium on circuits and systems …, 2010 | 44 | 2010 |
| A low-power, compact, adaptive logarithmic transimpedance amplifier operating over seven decades of current A Basu, RW Robucci, PE Hasler IEEE Transactions on Circuits and Systems I: Regular Papers 54 (10), 2167-2177, 2007 | 42 | 2007 |
| Ionotronic Halide Perovskite Drift‐Diffusive Synapses for Low‐Power Neuromorphic Computation RA John, N Yantara, YF Ng, G Narasimman, E Mosconi, D Meggiolaro, ... Advanced Materials 30 (51), 1805454, 2018 | 41 | 2018 |
| Low-power discrete Fourier transform for OFDM: A programmable analog approach S Suh, A Basu, C Schlottmann, PE Hasler, JR Barry IEEE Transactions on Circuits and Systems I: Regular Papers 58 (2), 290-298, 2010 | 41 | 2010 |
| Low-power, adaptive neuromorphic systems: Recent progress and future directions A Basu, J Acharya, T Karnik, H Liu, H Li, JS Seo, C Song IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (1), 6-27, 2018 | 40 | 2018 |
| Improved margin multi-class classification using dendritic neurons with morphological learning S Hussain, SC Liu, A Basu 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2640-2643, 2014 | 38 | 2014 |
| Liquid state machine with dendritically enhanced readout for low-power, neuromorphic VLSI implementations S Roy, A Banerjee, A Basu IEEE transactions on biomedical circuits and systems 8 (5), 681-695, 2014 | 36 | 2014 |
| Transistor channel dendrites implementing HMM classifiers P Hasler, S Kozoil, E Farquhar, A Basu 2007 IEEE International Symposium on Circuits and Systems, 3359-3362, 2007 | 36 | 2007 |
| A digitally assisted, signal folding neural recording amplifier Y Chen, A Basu, L Liu, X Zou, R Rajkumar, GS Dawe, M Je IEEE transactions on biomedical circuits and systems 8 (4), 528-542, 2014 | 33 | 2014 |
| A fully integrated architecture for fast and accurate programming of floating gates over six decades of current A Basu, PE Hasler IEEE transactions on very large scale integration (VLSI) systems 19 (6), 953-962, 2010 | 33 | 2010 |
Enyi YaoPh.D, Nanyang Technological UniversityVerified email at e.ntu.edu.sg
