Jingsheng Jason Cong

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Glenn ReinmanProfessor of Computer Science, UCLAVerified email at cs.ucla.edu
Zhiru ZhangCornell UniversityVerified email at cornell.edu
Deming ChenAbel Bliss Professor. University of Illinois at Urbana-ChampaignVerified email at illinois.edu
Bingjun XiaoUCLAVerified email at cs.ucla.edu
Guojie LuoPeking University, also affiliated with Pengcheng LaboratoryVerified email at pku.edu.cn
Zhenman FangAssistant Professor, Simon Fraser UniversityVerified email at sfu.ca
Guangyu SunCenter for Energy Efficient Computing and Applications, Peking UniversityVerified email at pku.edu.cn
Peng ZhangComputer Science, University of Califronia, Los AngelesVerified email at cs.ucla.edu
Peng LiPostDoc of Computer Science, UCLAVerified email at cs.ucla.edu
Lei HeProfessor of Electric Engineering, University of California, Los AngelesVerified email at ee.ucla.edu
YI ZOUUniversity of California Los AngeelsVerified email at cs.ucla.edu
Yiping FanXilinx Inc., AutoESL, UCLAVerified email at cs.ucla.edu
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at AustinVerified email at ece.utexas.edu
Peng WeiUniversity of California, Los AngelesVerified email at cs.ucla.edu
(Cody) Hao YuSenior Applied Scientist at Amazon AI, AWS | PhD of UCLAVerified email at amazon.com
Karthik GururajUniversity of California Los Angeles, Intel CorpVerified email at intel.com
Mau-Chung Frank ChangUniversity of California, Los AngelesVerified email at ee.ucla.edu
Chen ZhangDAMO Academy, AlibabaVerified email at alibaba-inc.com
Peipei ZhouAssistant Professor, University of Pittsburgh; PhD'19 UCLAVerified email at pitt.edu
Yan ZhangUCLAVerified email at cs.ucla.edu

Jingsheng Jason Cong

Volgenau Chair for Engineering Excellence, Computer Science and Electrical Engineering, University

Verified email at cs.ucla.edu - Homepage

customized computing for big data applications energy-efficient computing electronic design automation


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
Optimizing fpga-based accelerator design for deep convolutional neural networks C Zhang, P Li, G Sun, Y Guan, B Xiao, J Cong Proceedings of the 2015 ACM/SIGDA international symposium on field …, 2015	1882	2015
FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs J Cong, Y Ding IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994	935	1994
High-level synthesis for FPGAs: From prototyping to deployment J Cong, B Liu, S Neuendorffer, J Noguera, K Vissers, Z Zhang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011	836	2011
High-Level Synthesis for FPGAs: From Prototyping to Deployment Cong	836*
A thermal-driven floorplanning algorithm for 3D ICs J Cong, J Wei, Y Zhang IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004	522	2004
Caffeine: Toward uniformed representation and acceleration for deep convolutional neural networks C Zhang, G Sun, Z Fang, P Zhou, P Pan, J Cong IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018	504	2018
Performance optimization of VLSI interconnect layout J Cong, L He, CK Koh, PH Madden Integration 21 (1-2), 1-94, 1996	403	1996
CMP network-on-chip overlaid with multi-band RF-interconnect MF Chang, J Cong, A Kaplan, M Naik, G Reinman, E Socher, SW Tam 2008 IEEE 14th International Symposium on High Performance Computer …, 2008	344	2008
Minimizing computation in convolutional neural networks J Cong, B Xiao International conference on artificial neural networks, 281-290, 2014	341	2014
Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs X Wei, CH Yu, P Zhang, Y Chen, Y Wang, H Hu, Y Liang, J Cong Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017	322	2017
Application-specific instruction generation for configurable processor architectures J Cong, Y Fan, G Han, Z Zhang Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field …, 2004	302	2004
Combinational logic synthesis for LUT based field programmable gate arrays J Cong, Y Ding ACM Transactions on Design Automation of Electronic Systems (TODAES) 1 (2 …, 1996	283	1996
On area/depth trade-off in LUT-based FPGA technology mapping J Cong, Y Ding IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (2), 137-148, 1994	273	1994
An interconnect-centric design flow for nanometer technologies J Cong Proceedings of the IEEE 89 (4), 505-528, 2001	272	2001
Provably good performance-driven global routing J Cong, AB Kahng, G Robins, M Sarrafzadeh, CK Wong IEEE transactions on computer-aided design of integrated circuits and …, 1992	268	1992
FP-DNN: An automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates Y Guan, H Liang, N Xu, W Wang, S Shi, X Chen, G Sun, W Zhang, J Cong 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017	260	2017
Interconnect design for deep submicron ICs Z Pan, L He, CK Koh, KY Khoo 1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997	260	1997
A scalable micro wireless interconnect structure for CMPs SB Lee, SW Tam, I Pefkianakis, S Lu, MF Chang, C Guo, G Reinman, ... Proceedings of the 15th annual international conference on Mobile computing …, 2009	247	2009
Performance-driven interconnect design based on distributed RC delay model J Cong, KS Leung, D Zhou 30th ACM/IEEE Design Automation Conference, 606-611, 1993	247	1993
Architecture evaluation for power-efficient FPGAs F Li, D Chen, L He, J Cong Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field …, 2003	243	2003

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