Jingsheng Jason Cong

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Glenn ReinmanProfessor of Computer Science, UCLAVerified email at cs.ucla.edu
Zhiru ZhangCornell UniversityVerified email at cornell.edu
Deming ChenAbel Bliss Professor. University of Illinois at Urbana-ChampaignVerified email at illinois.edu
Bingjun XiaoUCLAVerified email at cs.ucla.edu
Zhenman FangAssistant Professor, Simon Fraser UniversityVerified email at sfu.ca
Guojie LuoPeking University, also affiliated with Pengcheng LaboratoryVerified email at pku.edu.cn
Guangyu SunSchool of Integrated Circuits, Peking UniversityVerified email at pku.edu.cn
Peng LiPostDoc of Computer Science, UCLAVerified email at cs.ucla.edu
Peng ZhangComputer Science, University of Califronia, Los AngelesVerified email at cs.ucla.edu
YI ZOUUniversity of California Los AngeelsVerified email at cs.ucla.edu
Yiping FanXilinx Inc., AutoESL, UCLAVerified email at cs.ucla.edu
Lei HeProfessor of Electric Engineering, University of California, Los AngelesVerified email at ee.ucla.edu
Peng WeiUniversity of California, Los AngelesVerified email at cs.ucla.edu
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at AustinVerified email at ece.utexas.edu
Cody (Hao) YuFounding Engineer at Boson AI | ex-Amazonian | UCLA PhD ‘19Verified email at boson.ai
Peipei ZhouAssistant Professor, University of Pittsburgh; PhD'19 CS UCLAVerified email at pitt.edu
Chen ZhangShanghai Jiao Tong UniversityVerified email at sjtu.edu.cn
Mau-Chung Frank ChangUniversity of California, Los AngelesVerified email at ee.ucla.edu
Karthik GururajUniversity of California Los Angeles, Intel CorpVerified email at intel.com
T F ChanPresident, King Abdullah University of Science & TechnologyVerified email at kaust.edu.sa

Jingsheng Jason Cong

Volgenau Chair for Engineering Excellence, Computer Science and Electrical Engineering, University

Verified email at cs.ucla.edu - Homepage

customized computing FPGA electronic design automation quantum computing


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Optimizing FPGA-based accelerator design for deep convolutional neural networks C Zhang, P Li, G Sun, Y Guan, B Xiao, J Cong Proceedings of the 2015 ACM/SIGDA international symposium on field …, 2015	2333	2015
High-level synthesis for FPGAs: From prototyping to deployment J Cong, B Liu, S Neuendorffer, J Noguera, K Vissers, Z Zhang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011	971	2011
High-Level Synthesis for FPGAs: From Prototyping to Deployment Cong	971*
FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs J Cong, Y Ding IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994	935	1994
Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks C Zhang, G Sun, Z Fang, P Zhou, J Cong Proceedings of the ACM Turing Award Celebration Conference-China 2023, 47-48, 2023	639	2023
A thermal-driven floorplanning algorithm for 3D ICs J Cong, J Wei, Y Zhang IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004	551	2004
Minimizing computation in convolutional neural networks J Cong, B Xiao International conference on artificial neural networks, 281-290, 2014	441	2014
Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs X Wei, CH Yu, P Zhang, Y Chen, Y Wang, H Hu, Y Liang, J Cong Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017	431	2017
Performance optimization of VLSI interconnect layout J Cong, L He, CK Koh, PH Madden Integration 21 (1-2), 1-94, 1996	408	1996
Scaling for edge inference of deep neural networks X Xu, Y Ding, SX Hu, M Niemier, J Cong, Y Hu, Y Shi Nature Electronics 1 (4), 216-222, 2018	367	2018
CMP network-on-chip overlaid with multi-band RF-interconnect MF Chang, J Cong, A Kaplan, M Naik, G Reinman, E Socher, SW Tam 2008 IEEE 14th International Symposium on High Performance Computer …, 2008	363	2008
FP-DNN: An automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates Y Guan, H Liang, N Xu, W Wang, S Shi, X Chen, G Sun, W Zhang, J Cong 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017	350	2017
Application-specific instruction generation for configurable processor architectures J Cong, Y Fan, G Han, Z Zhang Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field …, 2004	301	2004
Combinational logic synthesis for LUT based field programmable gate arrays J Cong, Y Ding ACM Transactions on Design Automation of Electronic Systems (TODAES) 1 (2 …, 1996	290	1996
An interconnect-centric design flow for nanometer technologies J Cong Proceedings of the IEEE 89 (4), 505-528, 2001	278	2001
On area/depth trade-off in LUT-based FPGA technology mapping J Cong, Y Ding Proceedings of the 30th International Design Automation Conference, 213-218, 1993	278	1993
Provably good performance-driven global routing J Cong, AB Kahng, G Robins, M Sarrafzadeh, CK Wong IEEE transactions on computer-aided design of integrated circuits and …, 1992	276	1992
A scalable micro wireless interconnect structure for CMPs SB Lee, SW Tam, I Pefkianakis, S Lu, MF Chang, C Guo, G Reinman, ... Proceedings of the 15th annual international conference on Mobile computing …, 2009	266	2009
mPL6: Enhanced multilevel mixed-size placement TF Chan, J Cong, JR Shinnerl, K Sze, M Xie Proceedings of the 2006 international symposium on Physical design, 212-214, 2006	261	2006
Interconnect design for deep submicron ICs Z Pan, L He, CK Koh, KY Khoo 1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997	259	1997

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