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Jin-Ku Kang
Jin-Ku Kang
Professor of ECE, Inha University, Korea
Verified email at inha.ac.kr - Homepage
Title
Cited by
Cited by
Year
Fabrication of a 2.5 Gbps× 4 channel optical micro-module for O-PCB application
HS Lee, S An, Y Kim, DK Kim, JK Kang, YW Choi, SG Lee, EH Lee
Microelectronic Engineering 83 (4-9), 1347-1351, 2006
302006
A resource efficient integer-arithmetic-only FPGA-based CNN accelerator for real-time facial emotion recognition
J Kim, JK Kang, Y Kim
IEEE Access 9, 104367-104381, 2021
272021
A CMOS high-speed data recovery circuit using the matched delay sampling technique
JK Kang, W Liu, RK Cavin
IEEE Journal of Solid-State Circuits 32 (10), 1588-1596, 1997
271997
An intra-panel interface with clock-embedded differential signaling for TFT-LCD systems
HK Jeon, YH Moon, JK Kang, LS Kim
Journal of Display Technology 7 (10), 562-571, 2011
252011
A 2.2-mW 20–135-MHz False-Lock-Free DLL for Display Interface in 0.15- CMOS
YH Moon, IS Kong, YS Ryu, JK Kang
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (8), 554-558, 2014
192014
Clock and data recovery circuit with two exclusive-OR phase frequency detector
DH Kim, JK Kang
Electronics Letters 36 (16), 1, 2000
172000
A CMOS clock and data recovery with two-XOR phase-frequency detector circuit
JK Kang, DH Kim
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001
162001
A 0.42–3.45 Gb/s referenceless clock and data recovery circuit with counter-based unrestricted frequency acquisition
KS Son, TJ An, YH Moon, JK Kang
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (6), 974-978, 2019
142019
A CMOS adiabatic logic for low power circuit design
H Song, J Kang
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System …, 2004
142004
A real time image processor for reproduction of gray levels in dark areas on plasma display panel (PDP)
CH Lee, SH Park, JK Kang, CW Kim
IEEE Transactions on Consumer Electronics 48 (4), 879-886, 2002
142002
A 1.0 Gbps CMOS oversampling data recovery circuit with fine delay generation method
JY Park, JK Kang
IEICE transactions on fundamentals of electronics, communications and …, 2000
142000
A self-timed wave pipelined adder using data align method
BH Lim, JK Kang
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 …, 2000
132000
A low power BPSK demodulator for wireless implantable biomedical devices
BP Wilkerson, JK Kang
2013 IEEE International Symposium on Circuits and Systems (ISCAS), 626-629, 2013
122013
An 8B/10B encoder with a modified coding table
Y Kim, J Kang
APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems, 1522-1525, 2008
122008
SSCG with Hershey-Kiss modulation profile using Dual Sigma-Delta modulators
HM Park, HB Jin, JK Kang
IEICE Electronics Express 7 (18), 1349-1353, 2010
112010
Fabrication and integration of micro/nano-scale polymer optical waveguides and devices for optical printed circuit board (O-PCB) application
EH Lee, SG Lee, SG Park, KH Kim, JK Kang, I Chin, YK Kwon, YW Choi
Organic Photonic Materials and Devices VII 5724, 112-123, 2005
112005
A CMOS 5.4/3.24‐Gbps Dual‐Rate CDR with Enhanced Quarter‐Rate Linear Phase Detector
JW Yoo, TH Kim, DK Kim, JK Kang
ETRI Journal 33 (5), 752-758, 2011
102011
A 0.32–2.7 Gb/s reference-less continuous-rate clock and data recovery circuit with unrestricted and fast frequency acquisition
NH Tho, HJ Lee, TJ An, JK Kang
IEEE Transactions on Circuits and Systems II: Express Briefs 68 (7), 2347-2351, 2021
92021
A two-step time-to-digital converter using ring oscillator time amplifier
M Kim, KS Son, N Kim, CH Rho, JK Kang
2018 International SoC Design Conference (ISOCC), 143-144, 2018
92018
A design of DisplayPort link layer
Y Kim, S Cha, J Kang
2008 International SoC Design Conference 2, II-45-II-48, 2008
92008
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Articles 1–20