Follow
Amir Roth
Amir Roth
Verified email at ee.doe.gov - Homepage
Title
Cited by
Cited by
Year
Dependence based prefetching for linked data structures
A Roth, A Moshovos, GS Sohi
Proceedings of the eighth international conference on Architectural support …, 1998
4291998
Speculative data-driven multithreading
A Roth, GS Sohi
Proceedings HPCA Seventh International Symposium on High-Performance …, 2001
4072001
Effective jump-pointer prefetching for linked data structures
A Roth, GS Sohi
Proceedings of the 26th annual international symposium on Computer …, 1999
2501999
Exploiting dead value information
MM Martin, A Roth, CN Fischer
Proceedings of 30th Annual International Symposium on Microarchitecture, 125-135, 1997
1371997
Store vulnerability window (SVW): Re-execution filtering for enhanced load optimization
A Roth
32nd International Symposium on Computer Architecture (ISCA'05), 458-468, 2005
1152005
DISE: A programmable macro engine for customizing applications
ML Corliss, EC Lewis, A Roth
ACM SIGARCH Computer Architecture News 31 (2), 362-373, 2003
1142003
Dataflow mini-graphs: Amplifying superscalar capacity and bandwidth
A Bracy, P Prahlad, A Roth
37th International Symposium on Microarchitecture (MICRO-37'04), 18-29, 2004
902004
Scalable store-load forwarding via store queue index prediction
T Sha, MMK Martin, A Roth
38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05 …, 2005
892005
Nosq: Store-load communication without a store queue
T Sha, MMK Martin, A Roth
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006
882006
Speculative multithreaded processors
GS Sohi, A Roth
IEEE Comput. Soc, 2001
852001
Register integration: a simple and efficient implementation of squash reuse
A Roth, GS Sohi
Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000
822000
Using DISE to protect return addresses from attack
ML Corliss, EC Lewis, A Roth
ACM SIGARCH Computer Architecture News 33 (1), 65-72, 2005
752005
iCFP: Tolerating all-level cache misses in in-order processors
A Hilton, S Nagarakatte, A Roth
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
732009
Reno: a rename-based instruction optimizer
V Petric, T Sha, A Roth
32nd International Symposium on Computer Architecture (ISCA'05), 98-109, 2005
722005
Grid-interactive efficient buildings technical report series: Whole-building controls, sensors, modeling, and analytics
A Roth, J Reyna
USDOE Office of Energy Efficiency and Renewable Energy (EERE), Energy …, 2019
682019
Improving virtual function call target prediction via dependence-based pre-computation
A Roth, A Moshovos, GS Sohi
Proceedings of the 13th international conference on Supercomputing, 356-364, 1999
611999
There's a measure for that!
A Roth, D Goldwasser, A Parker
Energy and Buildings 117, 321-331, 2016
532016
Prototyping the next generation energyplus simulation engine
M Wetter, TS Nouidui, D Lorenzetti, EA Lee, A Roth
Proceedings of the 3rd IBPSA Conference, Jeju island, South Korea, 27-29, 2015
462015
BOLT: Energy-efficient out-of-order latency-tolerant execution
A Hilton, A Roth
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
402010
Innovations in sensors and controls for building energy management: Research and development opportunities report for emerging technologies
M Sofos, JT Langevin, M Deru, E Gupta, KS Benne, D Blum, T Bohn, ...
National Renewable Energy Lab.(NREL), Golden, CO (United States), 2020
372020
The system can't perform the operation now. Try again later.
Articles 1–20