| Analysis of the source/drain parasitic resistance and capacitance depending on geometry of FinFET P Jay, AD Darji 2015 11th Conference on Ph. D. Research in Microelectronics and Electronics …, 2015 | 10 | 2015 |
| Assessment of interface traps in In0.53Ga0.47As FinFET with Gate-to-Source/Drain underlap for sub-14nm technology node to impede Short Channel effect J Pathak, A Darji IET Circuits, Devices & Systems, 2018 | 4 | 2018 |
| Investigation of TCADs Models for Characterization of Sub 16 nm InGaAs FinFET J Pathak, A Darji International Symposium on VLSI Design and Test, 279-286, 2017 | 4 | 2017 |
| Gain improvement of two stage OPAMP through body bias in 45nm CMOS technology S Kumar, P Jay, R Prasad International Journal of Research in Engineering and Technology 3 (4), 945-948, 2014 | 3 | 2014 |
| Analysis of 14nm technology node In0.53Ga0.47As nFinFET integrated with In0.52Al0.48As cap layer for high-speed circuits J Pathak, A Darji International Journal of Electronics 106 (10), 1514-1529, 2019 | 2 | 2019 |
| Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed Applications J Pathak, A Darji 2021 25th International Symposium on VLSI Design and Test (VDAT), 1-4, 2021 | 1 | 2021 |
| Curtailment of Propagation Delay in In0. 53Ga0. 47As Sub-14 nm FinFET by Integration of Doped/Undoped In0. 52 Al0. 48As Barrier Layer J Pathak, A Darji Journal of Nanoelectronics and Optoelectronics 14 (4), 505-512, 2019 | 1 | 2019 |
| Impact of Spacers in Raised Source/Drain 14 nm Technology Node In Ga As-nFinFET on Short Channel Effects J Pathak, AD Darji Advances in VLSI and Embedded Systems, 159-167, 2020 | | 2020 |
| Impact of Interface Traps and Parasitic Capacitance on Gate Capacitance of In0.53Ga0.47As-FinFET for sub 14nm Technology Node. J Pathak, A Darji International Journal of Nanoelectronics & Materials 12 (3), 2019 | | 2019 |
| Stability Analysis of SRAM Designed Using In0. 53Ga0. 47As nFinFET with Underlap Region J Pathak, AD Darji 2019 32nd International Conference on VLSI Design and 2019 18th …, 2019 | | 2019 |
| Assessment of sub14 nm technology node InGaAs nFinFET for high speed applications J Pathak Surat, 0 | | |
