| Verifying UML/OCL models using Boolean satisfiability M Soeken, R Wille, M Kuhlmann, M Gogolla, R Drechsler Proceedings of the Conference on Design, Automation and Test in Europe, 1341 …, 2010 | 184 | 2010 |
| Synthesis of reversible circuits with minimal lines for large functions M Soeken, R Wille, C Hilken, N Przigoda, R Drechsler Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 85-92, 2012 | 130 | 2012 |
| Assisted behavior driven development using natural language processing M Soeken, R Wille, R Drechsler International Conference on Modelling Techniques and Tools for Computer …, 2012 | 129 | 2012 |
| RevKit: A Toolkit for Reversible Circuit Design. M Soeken, S Frehse, R Wille, R Drechsler Multiple-Valued Logic and Soft Computing 18 (1), 55-65, 2012 | 129 | 2012 |
| RevKit: an open source toolkit for the design of reversible circuits M Soeken, S Frehse, R Wille, R Drechsler International Workshop on Reversible Computation, 64-76, 2011 | 92 | 2011 |
| Formal Verification of Integer Multipliers by Combining Grobner Basis with Logic Reduction A Sayed-Ahmed, D Große, U Kühne, M Soeken, R Drechsler | 91* | |
| Exact synthesis of majority-inverter graphs and its applications M Soeken, L Amaru, PE Gaillardon, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017 | 83 | 2017 |
| The EPFL logic synthesis libraries M Soeken, H Riener, W Haaswijk, E Testa, B Schmitt, G Meuli, F Mozafari, ... arXiv preprint arXiv:1805.05121, 2018 | 82 | 2018 |
| Verifying dynamic aspects of UML models. M Soeken, R Wille, R Drechsler DATE, 1077-1082, 2011 | 81 | 2011 |
| Reducing the number of lines in reversible circuits R Wille, M Soeken, R Drechsler Design Automation Conference (DAC), 2010 47th ACM/IEEE, 647-652, 2010 | 77 | 2010 |
| Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs S Shirinzadeh, M Soeken, PE Gaillardon, R Drechsler 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 948-953, 2016 | 75 | 2016 |
| Approximation-aware Rewriting of AIGs for Error Tolerant Applications A Chandrasekharan, M Soeken, D Große, R Drechsler | 70* | |
| BDD Minimization for Approximate Computing M Soeken, D Große, A Chandrasekharan, R Drechsler | 65* | |
| Deep Learning for Logic Optimization Algorithms WJ Haaswijk, E Collins, BLA Seguin, M Soeken, S Süsstrunk, F Kaplan, ... Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2018 | 64 | 2018 |
| Specification-driven model transformation testing E Guerra, M Soeken Software & Systems Modeling 14 (2), 623-644, 2015 | 63 | 2015 |
| Improving the mapping of reversible circuits to quantum circuits using multiple target lines R Wille, M Soeken, C Otterstedt, R Drechsler Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific …, 2013 | 63 | 2013 |
| Encoding OCL data types for SAT-based verification of UML/OCL models M Soeken, R Wille, R Drechsler International Conference on Tests and Proofs, 152-170, 2011 | 63 | 2011 |
| Trading off circuit lines and gate costs in the synthesis of reversible logic R Wille, M Soeken, DM Miller, R Drechsler Integration, the VLSI Journal 47 (2), 284-294, 2014 | 59 | 2014 |
| Improved quantum circuits for elliptic curve discrete logarithms T Häner, S Jaques, M Naehrig, M Roetteler, M Soeken International Conference on Post-Quantum Cryptography, 425-444, 2020 | 58 | 2020 |
| Quantum programming languages B Heim, M Soeken, S Marshall, C Granade, M Roetteler, A Geller, ... Nature Reviews Physics 2 (12), 709-722, 2020 | 55 | 2020 |
Rolf DrechslerProfessor at University of Bremen, Director DFKI Bremen, GermanyVerified email at uni-bremen.de
