| Binary-coded decimal digit multipliers G Jaberipur, A Kaivani IET Computers & Digital Techniques 1 (4), 377-381, 2007 | 101 | 2007 |
| Improving the speed of parallel decimal multiplication G Jaberipur, A Kaivani IEEE Transactions on Computers 58 (11), 1539-1552, 2009 | 98 | 2009 |
| Reversible barrel shifters S Gorgin, A Kaivani 2007 IEEE/ACS International Conference on Computer Systems and Applications …, 2007 | 37 | 2007 |
| Floating-point butterfly architecture based on binary signed-digit representation A Kaivani, S Ko IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (3 …, 2016 | 34 | 2016 |
| Improving the speed of decimal division A Kaivani, A Hosseiny, G Jaberipur IET computers & digital techniques 5 (5), 393-404, 2011 | 17 | 2011 |
| High-frequency sequential decimal multipliers A Kaivani, L Chen, S Ko 2012 IEEE International Symposium on Circuits and Systems, 3045-3048, 2012 | 13 | 2012 |
| Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture A Kaivani, G Jaberipur The Computer Journal 54 (11), 1798-1809, 2011 | 13 | 2011 |
| Fully redundant decimal addition and subtraction using stored-unibit encoding A Kaivani, G Jaberipur Integration, the VLSI journal 43 (1), 34-41, 2010 | 13 | 2010 |
| Area efficient floating-point FFT butterfly architectures based on multi-operand adders A Kaivani, SB Ko Electronics Letters 51 (12), 895-897, 2015 | 12 | 2015 |
| Improved design of high-frequency sequential decimal multipliers A Kaivani, L Han, SB Ko Electronics Letters 50 (7), 558-560, 2014 | 10 | 2014 |
| High-speed FFT processors based on redundant number systems A Kaivani, S Ko 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2237-2240, 2014 | 6 | 2014 |
| Decimal SRT Square Root: Algorithm and Architecture A Kaivani, SB Ko Circuits, Systems, and Signal Processing 32 (5), 2137-2150, 2013 | 6 | 2013 |
| Reversible implementation of Densely-Packed-Decimal converter to and from Binary-Coded-Decimal format using in IEEE-754R A Kaivani, AZ Alhosseini, S Gorgin, M Fazlali 9th International Conference on Information Technology (ICIT'06), 273-276, 2006 | 6 | 2006 |
| Area Efficient Sequential Decimal Fixed-point Multiplier L Han, A Kaivani, SB Ko Journal of Signal Processing Systems 75 (1), 39-46, 2014 | 4 | 2014 |
| Design of reduced quantum cost reversible BCD adder M Mohamadi, M Eshghi, A Kaivani IEEE EWDTS, Yerevan, 475-478, 2007 | 4 | 2007 |
| Decimal Division Algorithms: The Issue of Partial Remainders A Kaivani, SB Ko Journal of Signal Processing Systems 73 (2), 181-188, 2013 | 3 | 2013 |
| Decimal signed digit addition using stored transfer encoding A Kaivani, S Ko 2013 26th IEEE Canadian Conference on Electrical and Computer Engineering …, 2013 | 3 | 2013 |
| High-speed Co-processors Based on Redundant Number Systems A Kaivani University of Saskatchewan, 2015 | | 2015 |
Ghassem JaberipurProfessor for the Brain Pool Program in Chosun University, Gwangju, South Korea, SBU retiredVerified email at sbu.ac.ir
