Jose T. de Sousa
Jose T. de Sousa
INESC-ID / Tecnico University of Lisbon
Verified email at inesc-id.pt
TitleCited byYear
Defect level evaluation in an IC design environment
JT De Sousa, FM Gonçalves, JP Teixeira, C Marzocca, F Corsi, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1996
631996
A SAT Solver using Reconfigurable Hardware and Virtual Logic
M Abramovici, J.T. de Sousa
SAT 2000, Highlights of Satisfiability Research in the Year 2000,, 377-402, 2001
482001
A SAT solver using reconfigurable hardware and virtual logic
M Abramovici, JT De Sousa
Journal of Automated Reasoning 24 (1-2), 5-36, 2000
482000
IC Defects-Based Testability Analysis
JJT Sousa, FM Gonçalves, ...
International Test Conference (ITC), 500-509, 1991
431991
A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware
M Abramovici, JT de Sousa, D Saab
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 684-690, 1999
421999
A configurable hardware/software approach to SAT solving
JT de Sousa, JM Da Silva, M Abramovici
The 9th Annual IEEE Symposium on Field-Programmable Custom Computing …, 2001
402001
Virtual logic system for solving satisfiability problems using reconfigurable hardware
M Abramovici, JT De Sousa
US Patent 6,442,732, 2002
372002
Network core access architecture
JT De Sousa, NCC Lourenco, NGDR Ribeiro, VMG Martins, RJS Martins
US Patent 8,019,832, 2011
342011
Parallel backtracing for satisfiability on reconfigurable hardware
M Abramovici, JT De Sousa, DG Saab
US Patent 6,292,916, 2001
342001
Reducing the complexity of defect level modeling using the clustering effect
JT de Sousa, VD Agrawal
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2000
292000
Physical DFT for High Coverage of Realistic Faults
M Saraiva, P Casimiro, M Santos, JT Sousa, FM Gonçalves, I Teixeira, ...
Int. Test Conference (ITC), 642-651, 1992
261992
Fault Modeling and Defect Level Projections in Digital ICs
JT Sousa, FM Gonçalves, JP Teixeira, TW Williams
European Design and Test Conference (ED&TC), 436-442, 1994
211994
On implementing a configware/software SAT solver
NA Reis, JT de Sousa
Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom …, 2002
182002
Physical design of testable CMOS digital integrated circuits
JJHT de Sousa, FM Goncalves, JP Teixeira
IEEE Journal of Solid State Circuits 26 (7), 1064-1072, 1991
181991
Fault simulation using partially reconfigurable hardware
A Parreira, JP Teixeira, A Pantelimon, MB Santos, JT de Sousa
International Conference on Field Programmable Logic and Applications, 839-848, 2003
162003
Heuristic backtracking algorithms for SAT
A Bhalla, I Lynce, JT de Sousa, J Marques-Silva
Proceedings. 4th International Workshop on Microprocessor Test and …, 2003
152003
Layout-Driven Testability Enhancement
JP Teixeira, FM Gonçalves, JJT Sousa
European Test Conference, 101-109, 1991
141991
Boundary-scan interconnect diagnosis
JT De Sousa, PYK Cheung
Springer Science & Business Media, 2006
122006
Defect Level Estimation for Digital ICs
JJT Sousa, JP Teixeira
IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, 32-41, 1992
121992
Realistic fault list generation for physical testability assessment
JP Teixeira, FM Gonçalves, JJT Sousa
Proc. IEEE Workshop on Defect and Fault Tolerance in VLSI Systems, 131-140, 1990
121990
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