Tulika Mitra
Tulika Mitra
Professor of Computer Science, National University of Singapore
Verified email at comp.nus.edu.sg - Homepage
Title
Cited by
Cited by
Year
The worst-case execution-time problem—overview of methods and survey of tools
R Wilhelm, J Engblom, A Ermedahl, N Holsti, S Thesing, D Whalley, ...
ACM Transactions on Embedded Computing Systems (TECS) 7 (3), 1-53, 2008
20532008
Chronos: A timing analyzer for embedded software
X Li, Y Liang, T Mitra, A Roychoudhury
Science of Computer Programming 69 (1-3), 56-67, 2007
2472007
Scalable custom instructions identification for instruction-set extensible processors
P Yu, T Mitra
Proceedings of the 2004 international conference on Compilers, architecture …, 2004
2072004
WCET centric data allocation to scratchpad memory
V Suhendra, T Mitra, A Roychoudhury, T Chen
26th IEEE International Real-Time Systems Symposium (RTSS'05), 10 pp.-232, 2005
1912005
Hierarchical power management for asymmetric multi-core in dark silicon era
TS Muthukaruppan, M Pricopi, V Venkataramani, T Mitra, S Vishin
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-9, 2013
1882013
Exploring locking & partitioning for predictable shared caches on multi-cores
V Suhendra, T Mitra
Proceedings of the 45th annual Design Automation Conference, 300-303, 2008
1662008
Timing analysis of concurrent programs running on shared cache multi-cores
Y Li, V Suhendra, Y Liang, T Mitra, A Roychoudhury
2009 30th IEEE Real-Time Systems Symposium, 57-67, 2009
1642009
Modeling out-of-order processors for WCET analysis
X Li, A Roychoudhury, T Mitra
Real-Time Systems 34 (3), 195-227, 2006
164*2006
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
V Suhendra, C Raghavan, T Mitra
Proceedings of the 2006 international conference on Compilers, architecture …, 2006
1642006
Accurate estimation of cache-related preemption delay
HS Negi, T Mitra, A Roychoudhury
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware …, 2003
1472003
Modeling control speculation for timing analysis
X Li, T Mitra, A Roychoudhury
Real-Time Systems 29 (1), 27-58, 2005
141*2005
Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences
S Vajapeyam, T Mitra
ACM SIGARCH Computer Architecture News 25 (2), 1-12, 1997
1411997
Integrated CPU-GPU power management for 3D mobile games
A Pathania, Q Jiao, A Prakash, T Mitra
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
1332014
Modeling shared cache and bus in multi-cores for timing analysis
S Chattopadhyay, A Roychoudhury, T Mitra
Proceedings of the 13th international workshop on software & compilers for …, 2010
1232010
Characterizing embedded applications for instruction-set extensible processors
P Yu, T Mitra
Proceedings of the 41st annual Design Automation Conference, 723-728, 2004
1222004
Temperature aware task sequencing and voltage scaling
R Jayaseelan, T Mitra
2008 IEEE/ACM International Conference on Computer-Aided Design, 618-623, 2008
1112008
Estimating the worst-case energy consumption of embedded software
R Jayaseelan, T Mitra, X Li
12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS …, 2006
1092006
Power-performance modeling on asymmetric multi-cores
M Pricopi, TS Muthukaruppan, V Venkataramani, T Mitra, S Vishin
2013 International Conference on Compilers, Architecture and Synthesis for …, 2013
1032013
Efficient detection and exploitation of infeasible paths for software timing analysis
V Suhendra, T Mitra, A Roychoudhury, T Chen
Proceedings of the 43rd annual Design Automation Conference, 358-363, 2006
102*2006
Using formal techniques to debug the AMBA system-on-chip bus protocol
A Roychoudhury, T Mitra, SR Karri
2003 Design, Automation and Test in Europe Conference and Exhibition, 828-833, 2003
992003
The system can't perform the operation now. Try again later.
Articles 1–20