| Coarse-grained dynamically reconfigurable architecture with flexible reliability D Alnajiar, Y Ko, T Imagawa, H Konoura, M Hiromoto, Y Mitsuyama, ... 2009 International Conference on Field Programmable Logic and Applications …, 2009 | 49 | 2009 |
| Via-switch fpga: Highly dense mixed-grained reconfigurable architecture with overlay via-switch crossbars H Ochi, K Yamaguchi, T Fujimoto, J Hotate, T Kishimoto, T Higashi, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018 | 21 | 2018 |
| A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis T Imagawa, H Tsutsui, H Ochi, T Sato 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 701-706, 2013 | 21 | 2013 |
| Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing D Alnajjar, H Konoura, Y Mitsuyama, H Shimada, K Kobayashi, ... 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 313-316, 2013 | 12 | 2013 |
| Reliability-configurable mixed-grained reconfigurable array supporting C-based design and its irradiation testing H Konoura, D Alnajjar, Y Mitsuyama, H Shimada, K Kobayashi, ... IEICE Transactions on Fundamentals of Electronics, Communications and …, 2014 | 10 | 2014 |
| 33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications M Hashimoto, X Bai, N Banno, M Tada, T Sakamoto, J Yu, R Doi, Y Araki, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 502-504, 2020 | 8 | 2020 |
| High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA T Imagawa, H Tsutsui, H Ochi, T Sato International Symposium on Quality Electronic Design (ISQED), 538-545, 2013 | 5 | 2013 |
| MIMO-OFDM 無線通信における信号分離のためのパイプライン型逆行列演算回路のアーキテクチャ検討 今川隆司， 池下貴大， 筒井弘， 宮永喜一 研究報告システムと LSI の設計技術 (SLDM) 2017 (20), 1-4, 2017 | 4 | 2017 |
| A cost-effective selective tmr for coarse-grained reconfigurable architectures based on dfg-level vulnerability analysis T Imagawa, H Tsutsui, H Ochi, T Sato IEICE transactions on electronics 96 (4), 454-462, 2013 | 4 | 2013 |
| Reliability evaluation environment for exploring design space of coarse-grained reconfigurable architectures T Imagawa, M Hiromoto, H Ochi, T Sato IEICE transactions on fundamentals of electronics, communications and …, 2010 | 4 | 2010 |
| FiCC を用いた CMOS 互換な不揮発性メモリ素子の閾値電圧特性の測定ならびに読み出し方式検討 田中一平， 宮川尚之， 木村知也， 今川隆司， 越智裕之 DA シンポジウム 2019 論文集 2019, 9-14, 2019 | 3 | 2019 |
| Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain K Honda, T Imagawa, H Ochi 2017 30th IEEE International System-on-Chip Conference (SOCC), 80-85, 2017 | 3 | 2017 |
| FHD loss-less video communication over 8× 8 MIMO-OFDM Y Miyanaga, H Tsutsui, T Imagawa 2017 17th International Symposium on Communications and Information …, 2017 | 2 | 2017 |
| Image smoothing in the spatial domain using multigrid conjugate gradient methods based on accelerated iterative shrinkage D Kasauka, H Tsutsui, S Imai, T Imagawa, H Okuhata, Y Miyanaga 2016 Asia-Pacific Signal and Information Processing Association Annual …, 2016 | 2 | 2016 |
| Comparative evaluation of lifetime enhancement with fault avoidance on dynamically reconfigurable devices H Konoura, T Imagawa, Y Mitsuyama, M Hashimoto, T Onoye IEICE Transactions on Fundamentals of Electronics, Communications and …, 2014 | 2 | 2014 |
| A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor I Tanaka, N Miyagawa, T Kimura, T Imagawa, H Ochi IPSJ Transactions on System and LSI Design Methodology 16, 35-44, 2023 | 1 | 2023 |
| Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation M Hashimoto, X Bai, N Banno, M Tada, T Sakamoto, J Yu, R Doi, ... Japanese Journal of Applied Physics 61 (SM), SM0804, 2022 | 1 | 2022 |
| MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA T Imagawa, J Yu, M Hashimoto, H Ochi 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 838-843, 2021 | 1 | 2021 |
| Design and fabrication of characteristics measurement circuit for CMOS-compatible ultra-low-power non-volatile memory element using FiCC I Tanaka, N Miyagawa, T Kimura, T Imagawa, H Ochi IEICE Technical Report; IEICE Tech. Rep. 118 (334), 183-188, 2018 | 1 | 2018 |
| A Study on Quality Improvement of Frame Interpolation Method with High-Resolution and High-Frame Rate Video Using Foreground Elimination and Contour Extraction H Ihara, T Imagawa, H Uesaka, S Kokami, H Tsutsui, Y Miyanaga, H Ochi IEICE Technical Report; IEICE Tech. Rep. 117 (455), 55-60, 2018 | 1 | 2018 |
Masanori HashimotoKyoto UniversityVerified email at i.kyoto-u.ac.jp
