| Hygcn: A gcn accelerator with hybrid architecture M Yan, L Deng, X Hu, L Liang, Y Feng, X Ye, Z Zhang, D Fan, Y Xie 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 355 | 2020 |
| Rethinking the performance comparison between SNNS and ANNS L Deng, Y Wu, X Hu, L Liang, Y Ding, G Li, G Zhao, P Li, Y Xie Neural networks 121, 294-307, 2020 | 295 | 2020 |
| Deepsniffer: A dnn model extraction framework based on learning architectural hints X Hu, L Liang, S Li, L Deng, P Zuo, Y Ji, X Xie, Y Ding, C Liu, T Sherwood, ... Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 200* | 2020 |
| Tianjic: A unified and scalable chip bridging spike-based and continuous neural computation L Deng, G Wang, G Li, S Li, L Liang, M Zhu, Y Wu, Z Yang, Z Zou, J Pei, ... IEEE Journal of Solid-State Circuits 55 (8), 2228-2246, 2020 | 166 | 2020 |
| SpaceA: Sparse matrix vector multiplication on processing-in-memory accelerator X Xie, Z Liang, P Gu, A Basak, L Deng, L Liang, X Hu, Y Xie 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 98 | 2021 |
| A 28nm 29.2 TFLOPS/W BF16 and 36.5 TOPS/W INT8 reconfigurable digital CIM processor with unified FP/INT pipeline and bitwise in-memory booth multiplication for cloud deep … F Tu, Y Wang, Z Wu, L Liang, Y Ding, B Kim, L Liu, S Wei, Y Xie, S Yin 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 86 | 2022 |
| Comprehensive snn compression using admm optimization and activity regularization L Deng, Y Wu, Y Hu, L Liang, G Li, X Hu, Y Ding, P Li, Y Xie IEEE transactions on neural networks and learning systems 34 (6), 2791-2805, 2021 | 75 | 2021 |
| Exploring adversarial attack in spiking neural networks with spike-compatible gradient L Liang, X Hu, L Deng, Y Wu, G Li, Y Ding, P Li, Y Xie IEEE transactions on neural networks and learning systems 34 (5), 2569-2583, 2021 | 71 | 2021 |
| Crossbar-aware neural network pruning L Liang, L Deng, Y Zeng, X Hu, Y Ji, X Ma, G Li, Y Xie IEEE Access 6, 58324-58337, 2018 | 61 | 2018 |
| Rubik: A hierarchical architecture for efficient graph neural network training X Chen, Y Wang, X Xie, X Hu, A Basak, L Liang, M Yan, L Deng, Y Ding, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 49 | 2021 |
| Tetris: Tile-matching the tremendous irregular sparsity Y Ji, L Liang, L Deng, Y Zhang, Y Zhang, Y Xie Advances in neural information processing systems 31, 2018 | 46 | 2018 |
| A 28nm 15.59 µJ/token full-digital bitline-transpose CIM-based sparse transformer accelerator with pipeline/parallel reconfigurable modes F Tu, Z Wu, Y Wang, L Liang, L Liu, Y Ding, L Liu, S Wei, Y Xie, S Yin 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 466-468, 2022 | 45 | 2022 |
| Practical attacks on deep neural networks by memory trojaning X Hu, Y Zhao, L Deng, L Liang, P Zuo, J Ye, Y Lin, Y Xie IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 35 | 2020 |
| H2learn: High-efficiency learning accelerator for high-accuracy spiking neural networks L Liang, Z Qu, Z Chen, F Tu, Y Wu, L Deng, G Li, P Li, Y Xie IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 33 | 2021 |
| ReDCIM: Reconfigurable digital computing-in-memory processor with unified FP/INT pipeline for cloud AI acceleration F Tu, Y Wang, Z Wu, L Liang, Y Ding, B Kim, L Liu, S Wei, Y Xie, S Yin IEEE Journal of Solid-State Circuits 58 (1), 243-255, 2022 | 29 | 2022 |
| Sealing neural network models in encrypted deep learning accelerators P Zuo, Y Hua, L Liang, X Xie, X Hu, Y Xie 2021 58th ACM/IEEE Design Automation Conference (DAC), 1255-1260, 2021 | 27* | 2021 |
| TranCIM: Full-digital bitline-transpose CIM-based sparse transformer accelerator with pipeline/parallel reconfigurable modes F Tu, Z Wu, Y Wang, L Liang, L Liu, Y Ding, L Liu, S Wei, Y Xie, S Yin IEEE Journal of Solid-State Circuits 58 (6), 1798-1809, 2022 | 25 | 2022 |
| INSPIRE: in-storage private information retrieval via protocol and architecture co-design J Lin, L Liang, Z Qu, I Ahmad, L Liu, F Tu, T Gupta, Y Ding, Y Xie Proceedings of the 49th Annual International Symposium on Computer …, 2022 | 24 | 2022 |
| SemiMap: A semi-folded convolution mapping for speed-overhead balance on crossbars L Deng, L Liang, G Wang, L Chang, X Hu, X Ma, L Liu, J Pei, G Li, Y Xie IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 23 | 2018 |
| Effective and efficient batch normalization using a few uncorrelated data for statistics estimation Z Chen, L Deng, G Li, J Sun, X Hu, L Liang, Y Ding, Y Xie IEEE Transactions on Neural Networks and Learning Systems 32 (1), 348-362, 2020 | 20 | 2020 |
