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Yixiong Yang(杨一雄)
Yixiong Yang(杨一雄)
Verified email at mails.tsinghua.edu.cn
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Cited by
Year
Sticker: A 0.41-62.1 TOPS/W 8Bit neural network processor with multi-sparsity compatible convolution arrays and online tuning acceleration for fully connected layers
Z Yuan, J Yue, H Yang, Z Wang, J Li, Y Yang, Q Guo, X Li, MF Chang, ...
2018 IEEE symposium on VLSI circuits, 33-34, 2018
872018
STICKER: An energy-efficient multi-sparsity compatible accelerator for convolutional neural networks in 65-nm CMOS
Z Yuan, Y Liu, J Yue, Y Yang, J Wang, X Feng, J Zhao, X Li, H Yang
IEEE Journal of Solid-State Circuits 55 (2), 465-477, 2019
302019
A 130-nm ferroelectric nonvolatile system-on-chip with direct peripheral restore architecture for transient computing system
Y Liu, F Su, Y Yang, Z Wang, Y Wang, Z Li, X Li, R Yoshimura, T Naiki, ...
IEEE Journal of Solid-State Circuits 54 (3), 885-895, 2019
112019
14.2 A 65nm 24.7 µJ/Frame 12.3 mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width …
Z Yuan, Y Yang, J Yue, R Liu, X Feng, Z Lin, X Wu, X Li, H Yang, Y Liu
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 232-234, 2020
102020
A sparse-adaptive CNN processor with area/performance balanced N-way set-associate PE arrays assisted by a collision-aware scheduler
Z Yuan, J Wang, Y Yang, J Yue, Z Wang, X Feng, Y Wang, X Li, H Yang, ...
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 61-64, 2019
82019
A 4-Mbps 41-pJ/bit on-off keying transceiver for body-channel communication with enhanced auto loss compensation technique
J Zhao, J Mao, W Sun, Y Huang, Y Yang, H Yang, Y Liu
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 173-176, 2019
72019
A 2.2-GHz configurable direct digital frequency synthesizer based on LUT and rotation
Y Yang, X Shi, F Su, Z Wang, P Yang, H Yang, Y Liu
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (5), 1970-1980, 2018
42018
Multi-channel precision-sparsity-adapted inter-frame differential data codec for video neural network processor
Y Yang, Z Yuan, F Su, F Cheng, Z Yuan, H Yang, Y Liu
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2020
22020
A 2-GHz direct digital frequency synthesizer based on LUT and rotation
Y Yang, Z Wang, P Yang, MF Chang, MS Ho, H Yang, Y Liu
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
22018
Toward Low-Bit Neural Network Training Accelerator by Dynamic Group Accumulation
Y Yang, R Liu, W Sun, J Yue, H Yang, Y Liu
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 442-447, 2022
2022
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications
Y Yang, Y Liu, Z Yuan, W Sun, R Liu, J Wang, J Yue, X Feng, Z Yuan, X Li, ...
IEEE Journal of Solid-State Circuits, 2021
2021
Live Demonstration: A self-powered ultraviolet radiation monitoring platform based on nonvolatile processor
X Shi, Y Liu, Y Sun, Y Yang, K Qiu
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2018
2018
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